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s3c9454b/f9454b 8-bit cmos microcontroller user's manual revision 1
important notice the information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. this publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of samsung or others. samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by the customer's technical experts. samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the samsung product could create a situation where personal injury or death may occur. should the buyer purchase or use a samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that samsung was negligent regarding the design or manufacture of said product. s3c9454b/f9454b 8-bit cmos microcontroller user's manual, revision 1 publication number: 21- s3 - c9454b/f9454b -200409 ? 2004 samsung electronics all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of samsung electronics. samsung electronics' microcontroller business has been awarded full iso-14001 certification (bvq1 certificate no. fm9300). all semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. samsung electronics co., ltd. san #24 nongseo-ri, giheung-eup yongin-city, gyeonggi-do, korea c.p.o. box #37, suwon 440-900 tel: (0331) 209-1907 fax: (0331) 209-1899 home-page url: http://www.samsungsemi.com/ printed in the republic of korea
s3c9454b/f9454b microcontroller iii preface the s3c9454b/f9454b microcontroller user's manual is designed for application designers and programmers who are using the s3c9454b/f9454b microcontroller for application development. it is organized in two parts: part i programming model part ii hardware descriptions part i contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. it has six sections: chapter 1 product overview chapter 2 address spaces chapter 3 addressing modes chapter 4 control registers chapter 5 interrupt structure chapter 6 sam88rcri instruction set chapter 1, "product overview," is a high-level introduction to the s3c9454b/f9454b with a general product description, and detailed information about individual pin characteristics and pin circuit types. chapter 2, "address spaces," explains the s3c9454b/f9454b program and data memory, internal register file, and mapped control registers, and explains how to address them. chapter 2 also describes working register addressing, as well as system and user-defined stack operations. chapter 3, "addressing modes," contains detailed descriptions of the six addressing modes that are supported by the cpu. chapter 4, "control registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in standard format. you can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. chapter 5, "interrupt structure," describes the s3c9454b/f9454b interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in part ii. chapter 6, "sam88rcri instruction set," describes the features and conventions of the instruction set used for all s3c9-series microcontrollers. several summary tables are presented for orientation and reference. detailed descriptions of each instruction are presented in a standard format. each instruction description includes one or more practical examples of how to use the instruction when writing an application program. a basic familiarity with the information in part i will help you to understand the hardware module descriptions in part ii. if you are not yet familiar with the sam88rcri product family and are reading this manual for the first time, we recommend that you first read chapter 1-3 carefully. then, briefly look over the detailed information in chapters 4, 5, and 6. later, you can reference the information in part i as necessary. part ii contains detailed information about the peripheral components of the s3c9454b/f9454b microcontrollers. also included in part ii are electrical, mechanical, mtp, and development tools data. it has 10 chapters: chapter 7 clock circuit chapter 8 reset and power-down chapter 9 i/o ports chapter 10 basic timer and timer 0 chapter 11 8-bit pwm chapter 12 a/d converter chapter 13 electrical data chapter 14 mechanical data chapter 15 s3f945b mtp chapter 16 development tools two order forms are included at the back of this manual to facilitate customer order s3c9454b/f9454b microcon - trollers: the mask rom order form, and the mask option selection form. you can photocopy these forms, fill them out, and then forward them to your local samsung sales representative.
s3c9454b/f9454b microcontroller v table of contents part i ? programming model chapter 1 product overview sam88rcri product family ................................ ................................ ................................ ......................... 1-1 s3c9454b/f9454b microcontroller ................................ ................................ ................................ ............... 1-1 mtp ................................ ................................ ................................ ................................ ............................... 1-1 features ................................ ................................ ................................ ................................ ........................ 1-2 block diagram ................................ ................................ ................................ ................................ ............... 1-3 pin assignments ................................ ................................ ................................ ................................ ........... 1-4 pin descriptions ................................ ................................ ................................ ................................ ............ 1-6 pin circuits ................................ ................................ ................................ ................................ .................... 1-7 chapter 2 address spaces overview ................................ ................................ ................................ ................................ ....................... 2-1 program memory (rom) ................................ ................................ ................................ .............................. 2-2 register architecture ................................ ................................ ................................ ................................ ..... 2-5 common working register area (c0h?cfh) ................................ ................................ .............................. 2-7 system stack ................................ ................................ ................................ ................................ ................ 2-8 chapter 3 addressing modes overview ................................ ................................ ................................ ................................ ....................... 3-1 register addressing mode (r) ................................ ................................ ................................ ............. 3-2 indirect register addressing mode (ir) ................................ ................................ ............................... 3-3 indexed addressing mode (x) ................................ ................................ ................................ .............. 3-7 direct address mode (da) ................................ ................................ ................................ ................... 3-10 relative address mode (ra) ................................ ................................ ................................ ................ 3-12 immediate mode (im) ................................ ................................ ................................ ........................... 3-12
vi s3c9454b/f9454b microcontroller table of contents (continued) chapter 4 control registers overview ................................ ................................ ................................ ................................ ........................ 4-1 chapter 5 interrupt structure overview ................................ ................................ ................................ ................................ ........................ 5-1 interrupt processing control points ................................ ................................ ................................ ...... 5-1 enable/disable interrupt instructions (ei, di) ................................ ................................ ....................... 5-2 interrupt pending function types ................................ ................................ ................................ ......... 5-2 interrupt priority ................................ ................................ ................................ ................................ .... 5-2 interrupt source service sequence ................................ ................................ ................................ ...... 5-3 interrupt service routines ................................ ................................ ................................ .................... 5-3 generating interrupt vector addresses ................................ ................................ ................................ 5-3 s3c9454b/f9454b interrupt structure ................................ ................................ ................................ . 5-4 chapter 6 sam88rcri instruction set overview ................................ ................................ ................................ ................................ ........................ 6-1 register addressing ................................ ................................ ................................ ............................. 6-1 addressing modes ................................ ................................ ................................ ................................ 6-1 flags register (flags) ................................ ................................ ................................ ....................... 6-4 flag descriptions ................................ ................................ ................................ ................................ .. 6-4 instruction set notation ................................ ................................ ................................ ........................ 6-5 condition codes ................................ ................................ ................................ ................................ ... 6-9 instruction descriptions ................................ ................................ ................................ ........................ 6-10
s3c9454b/f9454b microcontroller vii table of contents (continued) part ii ? hardware descriptions chapter 7 clock circuit overview ................................ ................................ ................................ ................................ ....................... 7-1 main oscillator logic ................................ ................................ ................................ ............................ 7-1 clock status during power-down modes ................................ ................................ ............................ 7-2 system clock control register (clkcon) ................................ ................................ .......................... 7-2 chapter 8 reset and power-down system reset ................................ ................................ ................................ ................................ ................ 8-1 overview ................................ ................................ ................................ ................................ ............... 8-1 power-down modes ................................ ................................ ................................ ................................ ...... 8-3 stop mode ................................ ................................ ................................ ................................ ............ 8-3 idle mode ................................ ................................ ................................ ................................ .............. 8-3 hardware reset values ................................ ................................ ................................ ................................ 8-4 chapter 9 i/o ports overview ................................ ................................ ................................ ................................ ....................... 9-1 port data registers ................................ ................................ ................................ .............................. 9-2 port 0 ................................ ................................ ................................ ................................ .................... 9-3 port 1 ................................ ................................ ................................ ................................ .................... 9-7 port 2 ................................ ................................ ................................ ................................ .................... 9-9 chapter 10 basic timer and timers module overview ................................ ................................ ................................ ................................ .......... 10-1 basic timer (bt) ................................ ................................ ................................ ................................ ........... 10-2 basic timer control register (btcon) ................................ ................................ ............................... 10-2 basic timer function description ................................ ................................ ................................ ........ 10-3 timer 0 ................................ ................................ ................................ ................................ .......................... 10-7 timer 0 control registers (t0con) ................................ ................................ ................................ ..... 10-7 timer 0 function description ................................ ................................ ................................ ............... 10-8
viii s3c9454b/f9454b microcontroller table of contents (continued) chapter 11 8-bit pwm overview ................................ ................................ ................................ ................................ ........................ 11-1 function description ................................ ................................ ................................ ................................ ...... 11-1 pwm ................................ ................................ ................................ ................................ ..................... 11-1 pwm control register (pwmcon) ................................ ................................ ................................ ..... 11-5 chapter 12 a/d converter overview ................................ ................................ ................................ ................................ ........................ 12-1 using a/d pins for standard digital input ................................ ................................ ............................. 12-2 a/d converter control register (adcon) ................................ ................................ ............................ 12-2 internal reference voltage levels ................................ ................................ ................................ ........ 12-3 conversion timing ................................ ................................ ................................ ................................ 12-4 internal a/d conversion procedure ................................ ................................ ................................ ...... 12-5 chapter 13 electrical data overview ................................ ................................ ................................ ................................ ........................ 13-1 chapter 14 mechanical data overview ................................ ................................ ................................ ................................ ........................ 14-1 chapter 15 S3F9454B mtp overview ................................ ................................ ................................ ................................ ................................ ...... 15-1 operating mode characteristics ................................ ................................ ................................ ..................... 15-3 chapter 16 development tools overview ................................ ................................ ................................ ................................ ........................ 16-1 shine ................................ ................................ ................................ ................................ ................... 16-1 sama assembler ................................ ................................ ................................ ................................ .. 16-1 sasm86 ................................ ................................ ................................ ................................ ................ 16-1 hex2rom ................................ ................................ ................................ ................................ ............ 16-1 target boards ................................ ................................ ................................ ................................ ....... 16-2 mtps ................................ ................................ ................................ ................................ ...................... 16-2 tb9454b target board ................................ ................................ ................................ ......................... 16-3
s3c9454b/f9454b microcontroller ix list of figures figure title page number number 1-1 block diagram ................................ ................................ ................................ ......................... 1-3 1-2 pin assignment diagram (20-pin dip/sop/ssop package) ................................ ................. 1-4 1-3 pin assignment diagram (16-pin dip/sop/ssop package) ................................ ................. 1-5 1-5 pin circuit type a ................................ ................................ ................................ .................... 1-7 1-6 pin circuit type b ................................ ................................ ................................ .................... 1-7 1-7 pin circuit type c ................................ ................................ ................................ .................... 1-7 1-8 pin circuit type d ................................ ................................ ................................ .................... 1-7 1-9 pin circuit type e ................................ ................................ ................................ .................... 1-8 1-10 pin circuit type e-1 ................................ ................................ ................................ ................. 1-8 1-11 pin circuit type e-2 ................................ ................................ ................................ ................. 1-9 2-1 program memory address space ................................ ................................ ........................... 2-2 2-2 smart option ................................ ................................ ................................ ........................... 2-3 2-3 internal register file organization ................................ ................................ .......................... 2-6 2-4 16-bit register pairs ................................ ................................ ................................ ............... 2-7 2-5 stack operations ................................ ................................ ................................ ..................... 2-8 3-1 register addressing ................................ ................................ ................................ ........................... 3-2 3-2 working register addressing ................................ ................................ ................................ ........... 3-2 3-3 indirect register addressing to register file ................................ ................................ .................. 3-3 3-4 indirect register addressing to program memory ................................ ................................ ......... 3-4 3-5 indirect working register addressing to register file ................................ ................................ .. 3-5 3-6 indirect working register addressing to program or data memory ................................ ........... 3-6 3-7 indexed addressing to register file ................................ ................................ ................................ 3-7 3-8 indexed addressing to program or data memory with short offset ................................ ............ 3-8 3-9 indexed addressing to program or data memory with long offset ................................ ............ 3-9 3-10 direct addressing for load instructions ................................ ................................ ........................... 3-10 3-11 direct addressing for call and jump instructions ................................ ................................ .......... 3-11 3-12 relative addressing ................................ ................................ ................................ ............................ 3-12 3-13 immediate addressing ................................ ................................ ................................ ....................... 3-12 4-1 register description format ................................ ................................ ................................ .............. 4-4 5-1 s3f9-series interrupt type ................................ ................................ ................................ ..... 5-1 5-2 interrupt function diagram ................................ ................................ ................................ ...... 5-2 5-3 s3c9454b/f9454b interrupt structure ................................ ................................ ................... 5- 4 6-1 system flags register (flags) ................................ ................................ ............................. 6-4
x s3c9454b/f9454b microcontroller list of figures (continued) figure title page number number 7-1 main oscillator circuit (rc oscillator with internal capacitor) ................................ ............... 7-1 7-2 main oscillator circuit (crystal/ceramic oscillator) ................................ ................................ 7-1 7-3 system clock control register (clkcon) ................................ ................................ ............. 7-2 7-4 system clock circuit diagram ................................ ................................ ................................ . 7-3 8-1 reset block diagram ................................ ................................ ................................ ............... 8-2 8-2 timing for s3c9454b/f9454b after reset ................................ ................................ ........... 8-2 9-1 port data register format ................................ ................................ ................................ ....... 9-2 9-2 port 0 circuit diagram ................................ ................................ ................................ ............. 9-3 9-3 port 0 control register (p0conh, high byte) ................................ ................................ ........ 9-4 9-4 port 0 control register (p0conl, low byte) ................................ ................................ ......... 9-5 9-5 port 0 interrupt pending registers (p0pnd) ................................ ................................ ........... 9-6 9-6 port 1 circuit diagram ................................ ................................ ................................ ............. 9-7 9-7 port 1 control register (p1con) ................................ ................................ ............................ 9-8 9-8 port 2 circuit diagram ................................ ................................ ................................ ............. 9-9 9-9 port 2 control register (p2conh, high byte) ................................ ................................ ........ 9-10 9-10 port 2 control register (p2conl, low byte) ................................ ................................ .......... 9-11 10-1 basic timer control register (btcon) ................................ ................................ .................. 10-2 10-2 oscillation stabilization time on reset ................................ ................................ ................. 10-4 10-3 oscillation stabilization time on stop mode release ................................ ........................... 10-5 10-4 timer 0 control registers (t0con) ................................ ................................ ........................ 10-7 10-5 simplified timer 0 function diagram (interval timer mode) ................................ ................... 10-8 10-6 timer 0 timing diagram ................................ ................................ ................................ .......... 10-9 10-7 basic timer and timer 0 block diagram ................................ ................................ ................. 10-10 11-1 8-bit pwm basic waveform ................................ ................................ ................................ .... 11-3 11-2 8-bit extended pwm waveform ................................ ................................ ............................. 11-4 11-3 pwm control register (pwmcon) ................................ ................................ ........................ 11-5 11-4 pwm functional block diagram ................................ ................................ .............................. 11-6 12-1 a/d converter control register (adcon) ................................ ................................ .............. 12-2 12-2 a/d converter circuit diagram ................................ ................................ ................................ 12-3 12-3 a/ d converter data register (addatah/l) ................................ ................................ ........... 12-3 12-4 a/d converter timing diagram ................................ ................................ ............................... 12-4 12-5 recommended a/d converter circuit for highest absolute accuracy ................................ .... 12-5
s3c9454b/f9454b microcontroller xi list of figures (concluded) figure title page number number 13-1 input timing measurement points ................................ ................................ .......................... 13-4 13-2 operating voltage range ................................ ................................ ................................ ........ 13-6 13-3 schmitt trigger input characteristics diagram ................................ ................................ ....... 13-6 13-4 stop mode release timing when initiated by a reset ................................ ........................ 13-7 13-5 lvr reset timing ................................ ................................ ................................ ................... 13-9 14-1 20-dip-300a package dimensions ................................ ................................ ......................... 14-1 14-2 20-sop-375 package dimensions ................................ ................................ ......................... 14-2 14-3 20-ssop-225 package dimensions ................................ ................................ ....................... 14-3 14-4 16-dip-300a package dimensions ................................ ................................ ......................... 14-4 14-5 16-sop-bd300-sg package dimensions ................................ ................................ .............. 14-5 14-6 16-ssop-bd44 package dimensions ................................ ................................ .................... 14-6 15-1 pin assignment diagram (20-pin package) ................................ ................................ ............ 15-1 15-2 pin assignment diagram (16-pin package) ................................ ................................ ............ 15-2 16-1 smds2+ or sk-1000 product configuration ................................ ................................ ........... 16-2 16-2 tb9454b target board configuration ................................ ................................ ..................... 16-3 16-3 dip switch for smart option ................................ ................................ ................................ ... 16-5 16-4 20-pin connector for tb9454b ................................ ................................ ............................... 16-6 16-5 s3c9454b/f9454b probe adapter for 20-dip package ................................ ......................... 16-6
s3c9454b/f9454b microcontroller xiii list of tables table title page number number 1-1 s3c9454b/f9454b pin descriptions ................................ ................................ ...................... 1-6 2-1 register type summary ................................ ................................ ................................ .......... 2-5 4-1 system and peripheral control registers ................................ ................................ ........................ 4-2 6-1 instruction group summary ................................ ................................ ................................ .............. 6-2 6-2 flag notation conventions ................................ ................................ ................................ ................ 6-5 6-3 instruction set symbols ................................ ................................ ................................ ..................... 6-5 6-4 instruction notation conventions ................................ ................................ ................................ ...... 6-6 6-5 opcode quick reference ................................ ................................ ................................ .................. 6-7 6-6 condition codes ................................ ................................ ................................ ................................ .. 6-9 8-1 register values after a reset ................................ ................................ ................................ . 8- 4 9-1 s3c9454b/f9454b port configuration overview ................................ ................................ ... 9-1 9-2 port data register summary ................................ ................................ ................................ .. 9-2 11-1 pwm control and data registers ................................ ................................ ........................... 11-2 11-2 pwm output "stretch" values for extension data register (pwmdata.1?.0) ....................... 11-3 13-1 absolute maximum ratings ................................ ................................ ................................ .... 13-2 13-2 dc electrical characteristics ................................ ................................ ................................ ... 13-3 13-3 ac electrical characteristics ................................ ................................ ................................ ... 13-4 13-4 oscillator characteristics ................................ ................................ ................................ ......... 13-5 13-5 oscillation stabilization time ................................ ................................ ................................ .. 13-5 13-6 data retention supply voltage in stop mode ................................ ................................ ......... 13-7 13-7 a/d converter electrical characteris tics ................................ ................................ ................. 13-8 13-8 lvr circuit characteristics ................................ ................................ ................................ ..... 13-9 15-1 descriptions of pins used to read/write the flash rom ................................ ....................... 15-3 15-2 comparison of S3F9454B and s3c9454b features ................................ .............................. 15-3 15-3 operating mode selection criteria ................................ ................................ .......................... 15-3 16-1 power selection settings for tb9454b ................................ ................................ ................... 16-4 16-2 the smds2+ tool selection setting ................................ ................................ ....................... 16-4 16-3 using single header pins as the input path for external trigger sources ............................. 16-5
s3c9454b/f9454b microcontroller xv list of programming tips description page number chapter 2: address spaces smart option setting ................................ ................................ ................................ ................................ ..... 2-4 addressing the common working register area ................................ ................................ ......................... 2-7 standard stack operations using push and pop ................................ ................................ ............................... 2-9 chapter 8: reset and power-down sample s3c9454b/f9454b initialization routine ................................ ................................ ................................ .. 8-6 chapter 10: basic timer and timer 0 configuring the basic timer ................................ ................................ ................................ ................................ ...... 10-6 configuring timer 0 (interval mode) ................................ ................................ ................................ ........................ 10-11 chapter 11: 8-bit pwm programming the pwm module to sample specifications ................................ ................................ ................... 11-7 chapter 12: a/d converter configuring a/d converter ................................ ................................ ................................ ................................ ........ 12-6
s3c9454b/f9454b microcontroller xvii list of register descriptions register full register name page identifier number adcon a/d converter control register ................................ ................................ .................. 4-5 btcon basic timer control register ................................ ................................ ..................... 4-6 clkcon clock control register ................................ ................................ ............................... 4-7 flags system flags register ................................ ................................ ............................... 4-8 p0conh port 0 control register (high byte) ................................ ................................ ............ 4-9 p0conl port 0 control register (low byte) ................................ ................................ ............. 4-10 p0pnd port 0 interrupt pending register ................................ ................................ ............... 4-11 p1con port 1 control register ................................ ................................ ............................... 4-12 p2conh port 2 control register (high byte) ................................ ................................ ............ 4-13 p2conl port 2 control register (low byte) ................................ ................................ ............. 4-14 pwmcon pwm con trol register ................................ ................................ ............................... 4-15 stopcon stop mode control register ................................ ................................ ..................... 4-16 sym system mode register ................................ ................................ ............................... 4-16 t0con timer 0 control register ................................ ................................ .......................... 4-17
s3c9454b/f9454b microcontroller xix list of instruction descriptions instruction full instruction name page mnemonic number adc add with carry ................................ ................................ ................................ ............ 6-11 add add ................................ ................................ ................................ ............................. 6-12 and logical and ................................ ................................ ................................ ............... 6-13 call call procedure ................................ ................................ ................................ ............ 6-14 ccf complement carry flag ................................ ................................ ............................. 6-15 clr clear ................................ ................................ ................................ ........................... 6-16 com complement ................................ ................................ ................................ ............... 6-17 cp compare ................................ ................................ ................................ ..................... 6-18 dec decrement ................................ ................................ ................................ .................. 6-19 di disable interrupts ................................ ................................ ................................ ....... 6-20 ei enable interrupts ................................ ................................ ................................ ........ 6-21 idle idle operation ................................ ................................ ................................ ............. 6-22 inc increment ................................ ................................ ................................ ................... 6-23 iret interrupt return ................................ ................................ ................................ .......... 6-24 jp jump ................................ ................................ ................................ ........................... 6-25 jr jump relative ................................ ................................ ................................ ............. 6-26 ld load ................................ ................................ ................................ ........................... 6-27 ld load ................................ ................................ ................................ ........................... 6-28 ldc/lde load memory ................................ ................................ ................................ ............. 6-29 ldc/lde load memory ................................ ................................ ................................ ............. 6-30 ldcd/lded load memory and decrement ................................ ................................ .................... 6-31 ldci/ldei load memory and increment ................................ ................................ ..................... 6-32
xx s3c9454b/f9454b microcontroller list of instruction descriptions (continued) instruction full instruction name page mnemonic number nop no operation ................................ ................................ ................................ .............. 6-33 or logical or ................................ ................................ ................................ .................. 6-34 pop pop from stack ................................ ................................ ................................ .......... 6-35 push push to stack ................................ ................................ ................................ ............ 6-36 rcf reset carry flag ................................ ................................ ................................ ......... 6-37 ret return ................................ ................................ ................................ ......................... 6-38 rl rotate left ................................ ................................ ................................ .................. 6-39 rlc rotate l eft through carry ................................ ................................ .......................... 6-40 rr rotate right ................................ ................................ ................................ ................ 6-41 rrc rotate right through carry ................................ ................................ ........................ 6-42 sbc subtract with carry ................................ ................................ ................................ .... 6-43 scf set carry flag ................................ ................................ ................................ ............. 6-44 sra shift right arithmetic ................................ ................................ ................................ .. 6-45 stop stop operation ................................ ................................ ................................ ............ 6-46 sub subtract ................................ ................................ ................................ ...................... 6-47 tcm test complement under mask ................................ ................................ ................... 6-48 tm test under mask ................................ ................................ ................................ ........ 6-49 xor logical exclusive or ................................ ................................ ................................ .. 6-50
s3c9454b/f9454b product overview 1- 1 1 product overview sam88rcri product family samsung's sam88rcri family of 8-bit single-chip cmos microcontrollers offer a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. a address/data bus architecture and a large number of bit-configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included to support real-time operations. s3c9454b/f9454b microcontroller the s3c9454b/f9454b single-chip 8-bit microcontroller is designed for useful a/d converter application field. the s3c9454b/f9454b uses powerful sam88rcri cpu and s3c9454b/f9454b architecture. the internal register file is logically expanded to increase the on-chip register space. the s3c9454b/f9454b has 4k bytes of on-chip program rom and 208 bytes of ram. the s3c9454b/f9454b is a versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring simple timer/counter, pwm. in addition, the s3c9454b/f9454?s advanced cmos technology provides for low power consumption and wide operating voltage range. using the sam88rcri design approach, the following peripherals were integrated with the sam88rcri core: ? three configurable i/o ports (18 pins) ? four interrupt sources with one vector and one interrupt level ? one 8-bit timer/counter with time interval mode ? analog to digital converter with nine input channels(max) and 10-bit resolution ? one 8-bit pwm output the s3c9454b/f9454b microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, pwm, adc. s3c9454b/f9454b is available in a 20/16-pin dip and a 20/16-pin sop and a 20/16- pin ssop package. mtp the S3F9454B is an mtp (multi time programmable) version of the s3c9454b microcontroller. the S3F9454B has on-chip 4-kbyte multi-time programmable flash rom instead of masked rom. the S3F9454B is fully compatible with the s3c9454b, in function, in d.c. electrical characteristics and in pin configuration.
product overview s3c9454b/f9454b 1- 2 features cpu sam88rcri cpu core the sam88rcri core is low -end version of the current sam87 core. memory 4-kbyte internal program memory 208-byte general purpose register area instruction set 41 instructions the sam88rcri core provides all the sam87 core instruction except the word-oriented instruction, multiplication, division, and some one-byte instruction. instruction execution time 400 ns at 10 mhz f osc (minimum) interrupts 4 interrupt sources with one vector one interrupt level general i/o three i/o ports (max 18 pins) bit programmable ports 8-bit high-speed pwm 8-bit pwm 1-ch (max: 156 khz) 6-bit base + 2-bit extension built-in reset circuit low voltage detector for safe reset timer/counters one 8-bit basic timer for watchdog function one 8-bit timer/counter with time interval modes a/d converter nine analog input pins (max) 10-bit conversion resolution oscillation frequency 1 mhz to 10 mhz external crystal oscillator maximum 10 mhz cpu clock internal rc: 3.2 mhz (typ.), 0.5 mhz (typ.) in v dd = 5 v operating temperature range ? 25 c to + 85 c operating voltage range 2.0 v to 5.5 v (lvr disable) lvr to 5.5v (lvr enable) smart option package types s3c9454b/f9454b: ? 20-ssop-225 ? 20-dip-300a ? 20-sop-375 ? 16-sop-bd300-sg ? 16- dip-300a ? 16-ssop-bd44
s3c9454b/f9454b product overview 1- 3 block diagram 88rcri samri cpu port i/o and interrupt control 4 kb rom 208 byte register file timer 0 adc pwm x in x out osc basic timer adc0-adc8 p0.6/pwm port 0 port 2 port 1 p0.0/adc0/int0 p0.1/adc1/int1 p0.2/adc2 p0.7/adc7 ... p1.0 p1.1 p1.2 p2.0/t0 p2.1 p2.6 ... note: p1.2 is used as input only figure 1-1. block diagram
product overview s3c9454b/f9454b 1- 4 pin assignments s3c9454b/f9454b (20-dip-300a/ 20-sop-375/ 20-ssop-225) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 v ss x in /p1.0 x out /p1.1 nreset /p1.2 p2.0/t0 p2.1 p2.2 p2.3 p2.4 p2.5 v dd p0.0/adc0/int0 p0.1/adc1/int1 p0.2/adc2 p0.3/adc3 p0.4/adc4 p0.5/adc5 p0.6/adc6/pwm p0.7/adc7 p2.6/adc8/clo figure 1-2. pin assignment diagram (20-pin dip/sop/ssop package)
s3c9454b/f9454b product overview 1- 5 s3c9454b/f9454b (16-dip-300a/ 16-sop-bd300-sg/ 16-ssop-bd44) v dd p0.0/adc0/int0 p0.1/adc1/int1 p0.2/adc2 p0.3/adc3 p0.4/adc4 p0.5/adc5 p0.6/adc6/pwm 16 15 14 13 12 11 10 9 v ss x in /p1.0 x out /p1.1 nreset /p1.2 p2.0/t0 p2.1 p2.2 p2.3 1 2 3 4 5 6 7 8 figure 1-3. pin assignment diagram (16-pin dip/sop/ssop package)
product overview s3c9454b/f9454b 1- 6 pin descriptions table 1-1. s3c9454b/f9454b pin descriptions pin name input/ output pin description pin type share pins p0.0?p0.7 i/o bit-programmable i/o port for schmitt trigger input or push-pull output. pull-up resistors are assignable by software. port0 pins can also be used as a/d converter input, pwm output or external interrupt input. e-1 adc0?adc7 int0/int1 pwm p1.0?p1.1 i/o bit-programmable i/o port for schmitt trigger input or push-pull, open-drain output. pull-up resistors or pull-down resistors are assignable by software. e-2 x in, x out p1.2 i schmitt trigger input port b reset p2.0?p2.6 i/o bit-programmable i/o port for schmitt trigger input or push- pull, open-drain output. pull-up resistors are assignable by software. e e-1 ? adc8/clo t0 x in, x out ? crystal/ceramic, or rc oscillator signal for system clock. p1.0?p1.1 nreset i internal lvr or external reset b p1.2 v dd, v ss ? voltage input pin and ground ? clo o system clock output port e-1 p2.6 int0?int1 i external interrupt input port e-1 p0.0, p0.1 pwm o 8-bit high speed pwm output e-1 p0.6 t0 o timer0 match output e-1 p2.0 adc0?adc8 i a/d converter input e-1 e p0.0?p0.7 p2.6
s3c9454b/f9454b product overview 1- 7 pin circuits v dd in n-channel p-channel figure 1-5. pin circuit type a in figure 1-6. pin circuit type b v dd out output disable data figure 1-7. pin circuit type c i/o output disable data circuit type c pull-up enable v dd digital input figure 1-8. pin circuit type d
product overview s3c9454b/f9454b 1- 8 v dd i/o digital input p-ch v dd open-drain enable pull-up enable analog input enable adc output disable (input mode) data m u x alternative output p2.x p2conh p2conl n-ch figure 1-9. pin circuit type e v dd i/o digital input p-ch v dd pull-up enable output disable (input mode) data m u x alternative output p0.x p0conh n-ch analog input enable adc interrupt input figure 1-10. pin circuit type e-1
s3c9454b/f9454b product overview 1- 9 v dd i/o x in x out v dd open-drain enable output disable (input mode) p1.x digital input pull-up enable pull-down enable figure 1-11. pin circuit type e-2
product overview s3c9454b/f9454b 1- 10 notes
s3c9454b/f9454b address spaces 2- 1 2 address spaces overview the s3c9454b/f9454b microcontroller has two kinds of address space: ? internal program memory (rom) ? internal register file a 12-bit address bus supports program memory operations. a separate 8 -bit register bus carries addresses and data between the cpu and the internal register file. the s3c9454b/f9454b have 4-kbytes of mask-programmable on-chip program memory: which is configured as the internal rom mode, all of the 4-kbyte internal program memory is used. the s3c9454b/f9454b microcontroller has 208 general-purpose registers in its internal register file. twenty-six bytes in the register file are mapped for system and peripheral control functions.
address spaces s3c9454b/f9454b 2- 2 program memory (rom) normal operating mode the s3c9454b/f9454b have 4-kbytes (locations 0h?0fffh) of internal mask-programmable program memory. the first 2-bytes of the rom (0000h?0001h) are interrupt vector address. unused locations (0002h?00ffh except 3ch, 3dh, 3eh, 3fh) can be used as normal program memory. 3ch, 3dh, 3eh, 3fh is used smart option rom cell. the program reset address in the rom is 0100h. 4.095 1000h 0100h 60 4-kbyte program memory area interrupt vector 64 256 0040h 003ch 0000h (decimal) (hex) program start 0002h 0001h 2 1 0 smart option rom cell figure 2-1. program memory address space
s3c9454b/f9454b address spaces 2- 3 smart option smart option is the rom option for starting condition of the chip. the rom addresses used by smart option are from 003ch to 003fh. the s3c9454b/f9454b only use 003eh, 003fh. not used rom address 003ch, 003dh should be initialized to be initialized to 00h. the default value of rom is ffh (lvr enable, internal rc oscillator). rom address: 003dh .7 .6 .5 .4 .3 .2 .1 .0 msb lsb must be initialized to 00h. rom address: 003ch .7 .6 .5 .4 .3 .2 .1 .0 msb lsb must be initialized to 00h. rom address: 003eh .7 .6 .5 .4 .3 .2 .1 .0 msb lsb lvr enable/disable bit: 0 = disable 1 = enable lvr level selection bits: 11001 = 2.3 v 10010 = 3.0 v 01100 = 3.9 v not used rom address: 003fh .7 .6 .5 .4 .3 .2 .1 .0 msb lsb oscillator selection bits: 00 = external crystal/ ceramic oscillator 01 = external rc 10 = internal rc (0.5 mhz in v dd = 5 v) 11 = internal rc (3.2 mhz in v dd = 5 v) not used. notes: 1. when you use external oscillator, p1.0, p1.1 must be set to output port to prevent current consumption. 2. the value of unused bits of 3eh, 3fh is don't care. 3. when lvr is enabled, lvr level must be set to appropriate value, not default value. figure 2-2. smart option
address spaces s3c9454b/f9454b 2- 4 f programming tip ? smart option setting ; << interrupt vector address >> org 0000h vector 00h, int_9454 ; s3c9454b/f9454b has only one interrupt vector ; << smart option setting >> org 003ch db 00h ; 003ch, must be initialized to 0. db 00h ; 003dh, must be initialized to 0. db 0e7h ; 003eh, enable lvr (2.3 v) db 03h ; 003fh, internal rc (3.2 mhz in v dd = 5 v) ; << reset >> org 0100h reset: di ? ? ?
s3c9454b/f9454b address spaces 2- 5 register architecture the upper 64-bytes of the s3c9454b/f9454b's internal register file are addressed as working registers, system control registers and peripheral control registers. the lower 192-bytes of internal register file(00h?bfh) is called the general purpose register space . 234 registers in this space can be accessed; 208 are available for general- purpose use. for many sam88rcri microcontrollers, the addressable area of the internal register file is further expanded by additional register pages at the general purpose register space (00h?bfh: page0). this register file expansion is not implemented in the s3c9454b/f9454b, however. the specific register types and the area (in bytes) that they occupy in the internal register file are summarized in table 2-1. table 2-1. register type summary register type number of bytes cpu and system control registers 11 peripheral, i/o, and clock control and data registers 15 general-purpose registers (including the 16-bit common working register area) 208 total addressable bytes 234
address spaces s3c9454b/f9454b 2- 6 ffh c0h ~ bfh 00h 192 bytes 64 bytes of common area d0h cfh e0h dfh working registers system control registers peripheral control registers general purpose register file and stack area figure 2-3. internal register file organization
s3c9454b/f9454b address spaces 2- 7 common working register area (c0h?cfh) the sam88rcri register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. this16-byte address range is called common area. that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. typically, these working registers serve as temporary buffers for data operations between different pages. however, because the s3c9454b/f9454b uses only page 0, you can use the common area for any internal data operation. the register (r) addressing mode can be used to access this area registers are addressed either as a single 8-bit register or as a paired 16-bit register. in 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. msb rn lsb rn+1 n = even address figure 2-4. 16-bit register pairs f programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h?cfh, using working register addressing mode only. examples : 1. ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: ld r2,40h ; r2 (c2h) ? the value in location 40h 2. add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: add r3,#45h ; r3 (c3h) ? r3 + 45h
address spaces s3c9454b/f9454b 2- 8 system stack s3c9-series microcontrollers use the system stack for subroutine calls and returns and to store data. the push and pop instructions are used to control system stack operations. the s3c9454b/f9454b architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls and interrupts and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address is always decremented before a push operation and incremented after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-5. stack contents after a call instruction stack contents after an interrupt top of stack flags pch pcl pcl pch top of stack low address high address figure 2-5. stack operations stack pointer (sp) register location d9h contains the 8-bit stack pointer (sp) that is used for system stack operations. after a reset, the sp value is undetermined. because only internal memory space is implemented in the s3c9454b/f9454b, the sp must be initialized to an 8- bit value in the range 00h?0c0h. note in case a stack pointer is initialized to 00h, it is decreased to ffh when stack operation starts. this means that a stack pointer access invalid stack area. we recommend that a stack pointer is initialized to c0h to set upper address of stack to bfh.
s3c9454b/f9454b address spaces 2- 9 f programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld sp,#0c0h ; sp ? c0h (normally, the sp is set to c0h by the ; initialization routine) ? ? ? push sym ; stack address 0bfh ? sym push r15 ; stack address 0beh ? r15 push 20h ; stack address 0bdh ? 20h push r3 ; stack address 0bch ? r3 ? ? ? pop r3 ; r3 ? stack address 0bch pop 20h ; 20h ? stack address 0bdh pop r15 ; r15 ? stack address 0beh pop sym ; sym ? stack address 0bfh
address spaces s3c9454b/f9454b 2- 10 notes
s3c9454b/f9454b addressing mod es 3 - 1 3 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in sam88rcri instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the sam88rcr i instruction set supports six explicit addressing modes. not all of these addressing modes are available for each instruction. the addressing modes and their symbols are as follows: ? register (r) ? indirect register (ir) ? indexed (x) ? direct address (d a) ? relative address (ra) ? immediate (im)
addressing modes s3 c9454b/f9454b 3 - 2 register addressing mode (r) in register addressing mode, the operand is the content of a specified register (see figure 3 - 1). working register addressing differs from reg ister addressing because it uses an 16 - byte working register space in the register file and an 4 - bit register within that space (see figure 3 - 2). dst value used in instruction execution opcode operand 8-bit register file address point to one register in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3 - 1. register addressing dst opcode 4-bit working register point to the working register (1 of 8) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 and r2 are registers in the currently selected working register area. program memory register file src 3 lsbs operand rp0 or rp1 selected rp points to start of working register block msb point to rp0 to rp1 figure 3 - 2. working register addressing
s3c9454b/f9454b addressing mod es 3 - 3 indirect register ad dressing mode (ir) in indirect register (ir) addressing mode, the content o f the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space (see figures 3 - 3 through 3 - 6). you can use any 8 - bit register to indirectly address another register. any 16 - bit register pair can be used to indirectly address another memory location. 8-bit register file address one-operand instruction (example) dst address of operand used by instruction opcode address point to one register in register file sample instruction: rl @shift ; where shift is the label of an 8-bit register ddress program memory register file value used in instruction execution operand figure 3 - 3. indirect register addressing to register file
addressing modes s3 c9454b/f9454b 3 - 4 indirect register ad dressing mode (c ontinued ) dst opcode pair point to register pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register program memory 16-bit address points to program memory figure 3 - 4. indirect register addressing to program memory
s3c9454b/f9454b addressing mod es 3 - 5 indirect register ad dressing mode (c ontinued ) dst opcode operand 4-bit working register address point to the working register (1 of 16) sample instruction: or r6, @r2 program memory register file src 4 lsbs value used in instruction operand cfh c0h . . . . figure 3 - 5. indirect working register addressing to register file
addressing modes s3 c9454b/f9454b 3 - 6 indirect register ad dressing mode (c oncluded ) dst opcode 4-bit working register address sample instructions: lcd r5,@rr6 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4, r8 ; external data memory access program memory register file src value used in instruction operand example instruction references either program memory or data memory program memory or data memory next 3 bits point to working register pair (1 of 8) lsb selects register pair 16-bit address points to program memory or data memory cfh . . . . c0h figure 3 - 6. indirect working register a ddressing to program or data memory
s3c9454b/f9454b addressing mod es 3 - 7 indexed addressing m ode (x) indexed (x) addressing mode adds an offset value to a base addres s during instruction execution in order to calculate the effective operand address (see figure 3 - 7). you can use indexed addressing mode to access locations in the internal register file or in external memory. in short offset indexed addressing mode, the 8 - bit displacement is treated as a signed integer in the range ? 128 to + 127. this applies to external memory accesses only (see figure 3 - 8). for register file addressing, an 8 - bit base address provided by the instruction is added to an 8 - bit offset co ntained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8 - bit or 16 - bit offset given in the instruction is then added to the base address (see figure 3 - 9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory, external program memory, and for external data me mory, when implemented. dst opcode two-operand instruction example point to one of the working register (1 of 16) sample instruction: ld r0, #base[r1] ; where base is an 8-bit immediate value program memory register file 4 lsbs value used in instruction operand index x (offset) + src ~ ~ ~ ~ figure 3 - 7. indexed addressing to register file
addressing modes s3 c9454b/f9454b 3 - 8 indexed addressing m ode (c ontinued ) point to working register pair (1 of 8) lsb selects 16-bit address added to offset dst opcode program memory xs (offset) 4-bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + #04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 3 bits register pair src 8-bit 16-bit + program memory or data memory operand value used in instruction 16-bit register file figure 3 - 8. indexed addressing to program or data memory with short offset
s3c9454b/f9454b addressing mod es 3 - 9 indexed addressing m ode (c oncluded ) point to working register pair (1 of 8) lsb selects 16-bit address added to offset program memory 4-bit working register address sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + #1000h) are loaded into register r4. lde r4, #1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 3 bits register pair 16-bit 16-bit + program memory or datamemory operand value used in instruction 16-bit register file opcode xl h (offset) xl l (offset) dst src figure 3 - 9. indexed addressing to program or data memory with long offset
addressing modes s3 c9454b/f9454b 3 - 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16 - bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16 - bit destination address that is loaded into the pc whenever a jp or call instruction i s executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h)are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory figure 3 - 10. direct a ddressing for load instructions
s3c9454b/f9454b addressing mod es 3 - 11 direct address mode (c ontinued ) opcode program memory upper address byte program memory address used lower address byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3 - 11. direct addressing for call and jump instructions
addressing modes s3 c9454b/f9454b 3 - 12 relative address mod e (ra) in relative address (ra) mode, a two's - complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. the instructions that support ra addressing is jr. opcode program memory displacement program memory address used sample instructions: jr ult,$ + offset ; where offset is a value in the range + 127 to - 128 next opcode + signed displacement value current instruction current pc value figure 3 - 12. relative addressing immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) sample instruction: ld r0,#0aah opcode program memory operand figure 3 - 13. immediate addressing
s3c9454b/f9454b con trol registers 4- 1 4 control registers overview in this section, detailed descriptions of the s3c9454b/f9454b control registers are presented in an easy-to-read format. these descriptions will help familiarize you with the mapped locations in the register file. you can also use them as a quick-reference source when writing application programs. system and peripheral registers are summarized in table 4-1. figure 4-1 illustrates the important features of the standard register description format. control register descriptions are arranged in alphabetical order according to register mnemonic. more information about control registers is presented in the context of the various peripheral hardware descriptions in part ii of this manual.
control registers s 3c9454b/f9454b 4- 2 table 4-1. system and peripheral control registers register name mnemonic address & location reset value (bit) address r/w 7 6 5 4 3 2 1 0 timer 0 counter register t0cnt d0h r 0 0 0 0 0 0 0 0 timer 0 data register t0data d1h r/w 1 1 1 1 1 1 1 1 timer 0 control register t0con d2h r/w 0 0 ? ? 0 ? 0 0 location d3h is not mapped clock control register clkcon d4h r/w 0 ? ? 0 0 ? ? ? system flags register flags d5h r/w x x x x ? ? ? ? locations d6h?d8h are not mapped stack pointer register sp d9h r/w x x x x x x x x location dah is not mapped mds special register mdsreg dbh r/w 0 0 0 0 0 0 0 0 basic timer control register btcon dch r/w 0 0 0 0 0 0 0 0 basic timer counter btcnt ddh r 0 0 0 0 0 0 0 0 test mode control register ftstcon deh w ? ? 0 0 0 0 0 0 system mode register sym dfh r/w ? ? ? ? ? 0 0 0 notes: 1. ? : not mapped or not used, x: undefined 2. the factory test mode register, ftstcon, is for factory use only. its value should always be '00h' during the normal operation.
s3c9454b/f9454b con trol registers 4- 3 table 4-1. system and peripheral control registers (continued) register name mnemonic address r/w bit values after reset hex 7 6 5 4 3 2 1 0 port 0 data register p0 e0h r/w 0 0 0 0 0 0 0 0 port 1 data register p1 e1h r/w ? ? ? ? ? 0 0 0 port 2 data register p2 e2h r/w ? 0 0 0 0 0 0 0 locations e3h?e5h are not mapped port 0 control register (high byte) p0conh e6h r/w 0 0 0 0 0 0 0 0 port 0 control register p0conl e7h r/w 0 0 0 0 0 0 0 0 port 0 interrupt pending register p0pnd e8h r/w ? ? ? ? 0 0 0 0 port 1 control register p1con e9h r/w 0 0 ? ? 0 0 0 0 port 2 control register (high byte) p2conh eah r/w ? 0 0 0 0 0 0 0 port 2 control register (low byte) p2conl ebh r/w 0 0 0 0 0 0 0 0 locations ech?f1h are not mapped pwm data register pwmdata f2h r/w 0 0 0 0 0 0 0 0 pwm control register pwmcon f3h r/w 0 0 ? 0 0 0 0 0 stop .control register stopcon f4h r/w 0 0 0 0 0 0 0 0 locations f5h?f6h are not mapped a/d control register adcon f7h r/w 0 0 0 0 0 0 0 0 a/d converter data register ( high ) addatah f8h r x x x x x x x x a/d converter data register ( low ) addatal f9h r 0 0 0 0 0 0 x x locations fah?ffh are not mapped note: ? : not mapped or not used, x: undefined
control registers s 3c9454b/f9454b 4- 4 flags - system flags register .7 .6 .5 bit identifier reset value read/write r = read-only w = write-only r/w = read/write ' - ' = not used bit number: msb = bit 7 lsb = bit 0 description of the effect of specific bit settings reset value notation: '-' = not used 'x' = undetermind value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing d5h register address (hexadecimal) register name register id name of individual bit or related bits x r/w x r/w x r/w x r/w 0 r/w x r/w 0 r/w x r/w carry flag (c) 0 operation dose not generate a carry or borrow condition 1 operation generates carry-out or borrow into high-order bit7 zero flag 0 operation result is a non-zero value 1 operation result is zero sign flag 0 operation generates positive number (msb = "0") 1 operation generates negative number (msb = "1") .7 .6 .5 .4 .2 .3 .1 .0 figure 4-1. register description format
s3c9454b/f9454b con trol registers 4- 5 adcon ? a/d converter control register f7h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.4 a/d converter input pin selection bits 0 0 0 0 adc0 (p0.0) 0 0 0 1 adc1 (p0.1) 0 0 1 0 adc2 (p0.2) 0 0 1 1 adc3 (p0.3) 0 1 0 0 adc4 (p0.4) 0 1 0 1 adc5 (p0.5) 0 1 1 0 adc6 (p0.6) 0 1 1 1 adc7 (p0.7) 1 0 0 0 adc8 (p2.6) 1 0 0 1 connected with gnd internally 1 0 1 0 connected with gnd internally 1 0 1 1 connected with gnd internally 1 1 0 0 connected with gnd internally 1 1 0 1 connected with gnd internally 1 1 1 0 connected with gnd internally 1 1 1 1 connected with gnd internally .3 end-of-conversion status bit 0 a/d conversion is in progress 1 a/d conversion complete .2?.1 clock source selection bit (note) 0 0 f osc /16 (f osc 10 mhz) 0 1 f osc /8 (f osc 10 mhz) 1 0 f osc /4 (f osc 10 mhz) 1 1 f osc /1 (f osc 4 mhz) .0 conversion start bit 0 no meaning 1 a/d conversion start note: maximum adc clock input = 4 mhz.
control registers s 3c9454b/f9454b 4- 6 btcon ? basic timer control register dch bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.4 watchdog timer function enable bit 1 0 1 0 disable watchdog timer function others enable watchdog timer function .3?.2 basic timer input clock selection code 0 0 f osc /4096 0 1 f osc /1024 1 0 f osc /128 1 1 invalid setting .1 basic timer 8-bit counter clear bit 0 no effect 1 clear the basic timer counter value .0 basic timer divider clear bit 0 no effect 1 clear both dividers note: when you write a "1" to btcon.0 (or btcon.1), the basic timer counter (or basic timer divider) is cleared. the bit is then cleared automatically to "0".
s3c9454b/f9454b con trol registers 4- 7 clkcon ? clock control register d4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 ? ? 0 0 ? ? ? read/write r/w ? ? r/w r/w ? ? ? .7 oscillator irq wake-up function enable bit 0 enable irq for main system oscillator wake-up function 1 disable irq for main system oscillator wake-up function .6?.5 not used for s3c9454b/f9454b .4?.3 divided by selection bits for cpu clock frequency 0 0 divide by 16 (f osc /16) 0 1 divide by 8 (f osc /8) 1 0 divide by 2 (f osc /2) 1 1 non-divided clock (f osc ) .2?.0 not used for s3c9454b/f9454b
control registers s 3c9454b/f9454b 4- 8 flags ? system flags register d5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x ? ? ? ? read/write r/w r/w r/w r/w ? ? ? ? .7 carry flag (c) 0 operation does not generate a carry or borrow condition 1 operation generates a carry-out or borrow into high-order bit 7 .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is + 127 or 3 ? 128 1 operation result is > + 127 or < ? 128 .3?.0 not used for s3c9454b/f9454b
s3c9454b/f9454b con trol registers 4- 9 p0conh ? port 0 control register (high byte) e6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.6 port 0, p0.7/int7 configuration bits 0 0 schmitt trigger input; pull-up enable 0 1 schmitt trigger input 1 0 push-pull output 1 1 a/d converter input (adc7); schmitt trigger input off .5?.4 port 0, p0.6/adc6/pwm configuration bits 0 0 schmitt trigger input; pull-up enable 0 1 alternative function (pwm output) 1 0 push-pull output 1 1 a/d converter input (adc6); schmitt trigger input off .3?.2 port 0, p0.5/adc5 configuration bits 0 0 schmitt trigger input; pull-up enable 0 1 schmitt trigger input 1 0 push-pull output 1 1 a/d converter input (adc5); schmitt trigger input off .1?.0 port 0, p0.4/adc4 configuration bits 0 0 schmitt trigger input; pull-up enable 0 1 schmitt trigger input 1 0 push-pull output 1 1 a/d converter input (adc4); schmitt trigger input off
control registers s 3c9454b/f9454b 4- 10 p0conl ? port 0 control register (low byte) e7h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.6 port 0, p0.3/int3 configuration bits 0 0 schmitt trigger input 0 1 schmitt trigger input; pull-up enable 1 0 push-pull output 1 1 a/d converter input (adc3); schmitt trigger input off .5?.4 port 0, p0.2/adc2 configuration bits 0 0 schmitt trigger input 0 1 schmitt trigger input; pull-up enable 1 0 push-pull output 1 1 a/d converter input (adc2); schmitt trigger input off .3?.2 port 0, p0.1/adc1/int1 configuration bits 0 0 schmitt trigger input/falling edge interrupt input 0 1 schmitt trigger input; pull-up enable/falling edge interrupt input 1 0 push-pull output 1 1 a/d converter input (adc1); schmitt trigger input off .1?.0 port 0, p0.0/adc0/int0 configuration bits 0 0 schmitt trigger input/falling edge interrupt input 0 1 schmitt trigger input; pull-up enable/falling edge interrupt input 1 0 push-pull output 1 1 a/d converter input (adc0); schmitt trigger input off
s3c9454b/f9454b con trol registers 4- 11 p0pnd ? port 0 interrupt pending register e8h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7?.4 not used for the s3c9454b/f9454b .3 port 0.1/adc1/int1 interrupt enable bit 0 int1 falling edge interrupt disable 1 int1 falling edge interrupt enable .2 port 0.1/adc1/int1 interrupt pending bit 0 no interrupt pending (when read) 0 pending bit clear (when write) 1 interrupt is pending (when read) 1 no effect (when write) .1 port 0.0/adc0/int0 interrupt enable bit 0 int0 falling edge interrupt disable 1 int0 falling edge interrupt enable .0 port 0.0/adc0/int0 interrupt pending bit 0 no interrupt pending (when read) 0 pending bit clear (when write) 1 interrupt pending (when read) 1 no effect (when write)
control registers s 3c9454b/f9454b 4- 12 p1con ? port 1 control register e9h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 ? ? 0 0 0 0 read/write r/w r/w ? ? r/w r/w r/w r/w .7 part 1.1 n-channel open-drain enable bit 0 configure p1.1 as a push-pull output 1 configure p1.1 as a n-channel open-drain output .6 port 1.0 n-channel open-drain enable bit 0 configure p1.0 as a push-pull output 1 configure p1.0 as a n-channel open-drain output .5?.4 not used for s3c9454b/f9454b .3?.2 port 1, p1.1 interrupt pending bits 0 0 schmitt trigger input; 0 1 schmitt trigger input; pull-up enable 1 0 output 1 1 schmitt trigger input; pull-down enable .1?.0 port 1, p1.0 configuration bits 0 0 schmitt trigger input; 0 1 schmitt trigger input; pull-up enable 1 0 output 1 1 schmitt trigger input; pull-down enable note: when you use external oscillator, p1.0, p1.1 must be set to output port to prevent current consumption.
s3c9454b/f9454b con trol registers 4- 13 p2conh ? port 2 control register (high byte) eah bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? 0 0 0 0 0 0 0 read/write ? r/w r/w r/w r/w r/w r/w r/w .7 not used for the s3c9454b/f9454b .6?.4 port 2, p2.6/adc8/clo configuration bits 0 0 0 schmitt trigger input; pull-up enable 0 0 1 schmitt trigger input 0 1 x adc input 1 0 0 push-pull output 1 0 1 open-drain output; pull-up enable 1 1 0 open-drain output 1 1 1 alternative function; clo output .3?.2 port 2, 2.5 configuration bits 0 0 schmitt trigger input; pull-up enable 0 1 schmitt trigger input 1 0 push-pull output 1 1 open-drain output .1?.0 port 2, 2.4 configuration bits 0 0 schmitt trigger input; pull-up enable 0 1 schmitt trigger input 1 0 push-pull output 1 1 open-drain output note: when noise problem is important issue, you had better not use clo output.
control registers s 3c9454b/f9454b 4- 14 p2conl ? port 2 control register (low byte) ebh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.6 part 2, p2.3 configuration bits 0 0 schmitt trigger input; pull-up enable 0 1 schmitt trigger input 1 0 push-pull output 1 1 open-drain output .5?.4 port 2, p2.2 configuration bits 0 0 schmitt trigger input; pull-up enable 0 1 schmitt trigger input 1 0 push-pull output 1 1 open-drain output .3?.2 port 2, p2.1 configuration bits 0 0 schmitt trigger input; pull-up enable 0 1 schmitt trigger input 1 0 push-pull output 1 1 open-drain output .1?.0 port 2, p2.0 configuration bits 0 0 schmitt trigger input; pull-up enable 0 1 schmitt trigger input 1 0 push-pull output 1 1 t0 match output
s3c9454b/f9454b con trol registers 4- 15 pwmcon ? pwm control register e3h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 ? 0 0 0 0 0 read/write r/w r/w ? r/w r/w r/w r/w r/w .7?.6 pwm input clock selection bits 0 0 f osc /64 0 1 f osc /8 1 0 f osc /2 1 1 f osc /1 .5 not used for s3c9454b/f9454b .4 pwmdata reload interval selection bit 0 reload from 8-bit up counter overflow 1 reload from 6-bit up counter overflow .3 pwm counter clear bit 0 no effect 1 clear the pwm counter (when write) .2 pwm counter enable bit 0 stop counter 1 start (resume countering) .1 pwm overflow interrupt enable bit (8-bit overflow) 0 disable interrupt 1 enable interrupt .0 pwm overflow interrupt pending bit 0 no interrupt pending (when read) 0 clear pending bit (when write) 1 interrupt is pending (when read) 1 no effect (when write) note: pwmcon.3 is not auto-cleared. you must pay attention when clear pending bit. (refer to page 11-8).
control registers s 3c9454b/f9454b 4- 16 stopcon ? stop mode control register e4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.0 watchdog timer function enable bit 10100101 enable stop instruction other value disable stop instruction note: when stopcon register is not #0a5h value, if you use stop instruction, pc is changed to reset address. sym ? system mode register dfh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7?.3 not used for s3c9454b/f9454b .3 global interrupt enable bit 0 disable all interrupts 1 enable all interrupt .2?.0 page select bits 0 0 0 page 0 0 0 1 page 1 (not used for s3c9454b/f9454b ) 0 1 0 page 2 (not used for s3c9454b/f9454b ) 0 1 1 page 3 (not used for s3c9454b/f9454b )
s3c9454b/f9454b con trol registers 4- 17 t0con ? timer 0 control register f4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 ? ? 0 ? 0 0 read/write r/w r/w ? ? r/w ? r/w r/w .7?.6 timer 0 input clock selection bits 0 0 f osc /4096 0 1 f osc /256 1 0 f osc /8 1 1 f osc /1 .5?.4 not used for the s3c9454b/f9454b .3 timer 0 counter clear bit 0 no effect 1 clear the timer 0 counter (when write) .2 not used for the s3c9454b/f9454b .1 timer 0 interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer 0 interrupt pending bit (capture or match interrupt) 0 no interrupt pending (when read) 0 clear pending bit (when write) 1 interrupt is pending (when read) 1 no effect (when write) notes: 1. t0con.3 is not auto-cleared. you must pay attention when clear pending bit. (refer to page 10-12) 2. to use t0 match output, you set t0con.3 to "1". (refer to page 10-7)
control registers s 3c9454b/f9454b 4- 18 notes
s3c9454b/f9454b interrupt structure 5- 1 5 interrupt structure overview the sam88rcri interrupt structure has two basic components: a vector, and sources. the number of interrupt sources can be serviced through an interrupt vector which is assigned in rom address 0000h. vector sources 0000h 0001h notes: 1. the sam88rcri interrupt has only one vector address (0000h-0001h). 2. the numbern of sn value is expandable. s1 s2 s3 sn figure 5-1. s3f9-series interrupt type interrupt processing control points interrupt processing can be controlled in two ways: either globally, or by specific interrupt level and source. the system-level control points in the interrupt structure are therefore: ? global interrupt enable and disable (by ei and di instructions) ? interrupt source enable and disable set tings in the corresponding peripheral control register(s)
interrupt structure s3c9454b/f9454b 5- 2 enable/disable interrupt instructions (ei, di) the system mode register, sym (dfh), is used to enable and disable interrupt processing. sym.3 is the enable and disable bit for global interrupt processing respectively, by modifying sym.3. an enable interrupt (ei) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. although you can manipulate sym.3 directly to enable and disable interrupts during normal operation, we recommend that you use the ei and di instructions for this purpose. interrupt pending function types when the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (iret) occurs. interrupt priority because there is not a interrupt priority register in sam88rcri, the order of service is determined by a sequence of source which is executed in interrupt service routine. interrupt pending register global interrupt control (ei, di instruction) vector interrupt cycle interrpt priority is determind by software polling method "ei" instruction execution reset source interrupts source interrupt enable s r q figure 5-2. interrupt function diagram
s3c9454b/f9454b interrupt structure 5- 3 interrupt source service sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request pending bit to "1". 2. the cpu generates an interrupt acknowledge si gnal. 3. the service routine starts and the source's pending flag is cleared to "0" by software. 4. interrupt priority must be determined by software polling method. interrupt service routines before an interrupt request can be serviced, the following conditions must be met: ? interrupt processing must be enabled (ei, sym.3 = "1") ? interrupt must be enabled at the interrupt's source (peripheral control register) if all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the global interrupt enable bit in the sym register (di, sym.3 = "0") to disable all subsequent interrupts. 2. save the program counter and status flags to stack. 3. branch to the interrupt vector to fetch the service routine's address. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, an interrupt return instruction (iret) occurs. the iret restores the pc and status flags and sets sym.3 to "1" (ei), allowing the cpu to process the next interrupt request. generating interrupt vector addresses the interrupt vector area in the rom contains the address of the interrupt service routine. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to stack. 2. push the program counter's high-byte value to stack. 3. push the flags register values to stack. 4. fetch the service routine's high-byte address from the vector address 0000h. 5. fetch the service routine's low-byte address from the vector address 0001h. 6. branch to the service routine specified by the 16-bit vector address.
interrupt structure s3c9454b/f9454b 5- 4 s3c9454b/f9454b interrupt structure the s3c9454b/f9454b microcontroller has four peripheral interrupt sources: ? pwm overflow ? timer 0 match ? p0.0 external interrupt ? p0.1 external interrupt vector pending bits enable/disable source t0con.0 sym.2 (ei, di) pwmcon.0 p0pnd.0 p0pnd.2 t0con.1 pwmcon.1 p0pnd.1 p0pnd.3 timer 0 match pwm overflow p0.0 external interrupt p0.1 external interrupt 0000h 0001h figure 5-3. s3c9454b/f9454b interrupt structure
s3c9454b/f9454b sam88rcri instruction set 6- 1 6 sam88rcri instruction set overview the sam88rcri instruction set is designed to support the large register file. it includes a full complement of 8-bit arithmetic and logic operations. there are 41 instructions. no special i/o instructions are necessary because i/o control and data registers are mapped directly into the register file. flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the sam88rcri instruction set. register addressing to access an individual register, an 8-bit address in the range 0?255 or the 4-bit address of a working register is specified. paired registers can be used to construct 13-bit program memory or data memory addresses. for detailed information about register addressing, please refer to chapter 2, "address spaces". addressing modes there are six addressing modes: register (r), indirect register (ir), indexed (x), direct (da), relative (ra), and immediate (im). for detailed descriptions of these addressing modes, please refer to chapter 3, "addressing modes".
sam88rcri instruction set s3c9454b/f945 4b 6- 2 table 6-1. instruction group summary mnemonic operands instruction load instructions clr dst clear ld dst,src load ldc dst,src load program memory lde dst,src load external data memory ldcd dst,src load program memory and decrement lded dst,src load external data memory and decrement ldci dst,src load program memory and increment ldei dst,src load external data memory and increment pop dst pop from stack push src push to stack arithmetic instructions adc dst,src add with carry add dst,src add cp dst,src compare dec dst decrement inc dst increment sbc dst,src subtract with carry sub dst,src subtract logic instructions and dst,src logical and com dst complement or dst,src logical or xor dst,src logical exclusive or
s3c9454b/f9454b sam88rcri instruction set 6- 3 table 6-1. instruction group summary (continued) mnemonic operands instruction program control instructions call dst call procedure iret interrupt return jp cc,dst jump on condition code jp dst jump unconditional jr cc,dst jump relative on condition code ret return bit manipulation instructions tcm dst,src test complement under mask tm dst,src test under mask rotate and shift instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic cpu control instructions ccf complement carry flag di disable interrupts ei enable interrupts idle enter idle mode nop no operation rcf reset carry flag scf set carry flag stop enter stop mode
sam88rcri instruction set s3c9454b/f945 4b 6- 4 flags register (flags) the flags register flags contains eight bits that describe the current status of cpu operations. four of these bits, flags.4?flags.7, can be tested and used with conditional jump instructions; flags register can be set or reset by instructions as long as its outcome does not affect the flags, such as, load instruction. logical and arithmetic instructions such as, and, or, xor, add, and sub can affect the flags register. for example, the and instruction updates the zero, sign and overflow flags based on the outcome of the and instruction. if the and instruction uses the flags register as the destination, then simultaneously, two write will occur to the flags register producing an unpredictable result. system flags register (flags) d5h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb carry flag (c) zero flag (z) sign flag (s) overflow flag (v) not mapped figure 6-1. system flags register (flags) flag descriptions 030303 overflow flag (flags.4, v) the v flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ? 128. it is also cleared to "0" following logic operations. sign flag (flags.5, s) following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the msb of the result. a logic zero indicates a positive number and a logic one indicates a negative number. zero flag (flags.6, z) for arithmetic and logic operations, the z flag is set to "1" if the result of the operation is zero. for operations that test register bits, and for shift and rotate operations, the z flag is set to "1" if the result is logic zero. carry flag (flags.7, c) the c flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (msb). after rotate and shift operations, it contains the last value shifted out of the specified register. program instructions can set, clear, or complement the carry flag.
s3c9454b/f9454b sam88rcri instruction set 6- 5 instruction set notation table 6-2. flag notation conventions flag description c carry flag z zero flag s sign flag v overflow flag 0 cleared to logic zero 1 set to logic one * set or cleared according to operation ? value is unaffected x value is undefined table 6-3. instruction set symbols symbol description dst destination operand src source operand @ indirect register address prefix pc program counter flags flags register (d5h) # immediate operand or register address prefix h hexadecimal number suffix d decimal number suffix b binary number suffix opc opcode
sam88rcri instruction set s3c9454b/f945 4b 6- 6 table 6-4. instruction notation conventions notation description actual operand range cc condition code see list of condition codes in table 6-6. r working register only rn (n = 0?15) rr working register pair rrp (p = 0, 2, 4, ..., 14) r register or working register reg or rn (reg = 0?255, n = 0?15) rr register pair or working register pair reg or rrp (reg = 0?254, even number only, where p = 0, 2, ..., 14) ir indirect working register only @rn (n = 0?15) ir indirect register or indirect working register @rn or @reg (reg = 0?255, n = 0?15) irr indirect working register pair only @rrp (p = 0, 2, ..., 14) irr indirect register pair or indirect working register pair @rrp or @reg (reg = 0?254, even only, where p = 0, 2, ..., 14) x indexed addressing mode #reg[rn] (reg = 0?255, n = 0?15) xs indexed (short offset) addressing mode #addr[rrp] (addr = range ? 128 to + 127, where p = 0, 2, ..., 14) xl indexed (long offset) addressing mode #addr [rrp] (addr = range 0?8191, where p = 0, 2, ..., 14) da direct addressing mode addr (addr = range 0?8191) ra relative addressing mode addr (addr = number in the range + 127 to ? 128 that is an offset relative to the address of the next instruction) im immediate addressing mode #data (data = 0?255)
s3c9454b/f9454b sam88rcri instruction set 6- 7 table 6-5. opcode quick reference opcode map lower nibble (hex) ? 0 1 2 3 4 5 6 7 u 0 dec r1 dec ir1 add r1,r2 add r1,ir2 add r2,r1 add ir2,r1 add r1,im p 1 rlc r1 rlc ir1 adc r1,r2 adc r1,ir2 adc r2,r1 adc ir2,r1 adc r1,im p 2 inc r1 inc ir1 sub r1,r2 sub r1,ir2 sub r2,r1 sub ir2,r1 sub r1,im e 3 jp irr1 sbc r1,r2 sbc r1,ir2 sbc r2,r1 sbc ir2,r1 sbc r1,im r 4 or r1,r2 or r1,ir2 or r2,r1 or ir2,r1 or r1,im 5 pop r1 pop ir1 and r1,r2 and r1,ir2 and r2,r1 and ir2,r1 and r1,im n 6 com r1 com ir1 tcm r1,r2 tcm r1,ir2 tcm r2,r1 tcm ir2,r1 tcm r1,im i 7 push r2 push ir2 tm r1,r2 tm r1,ir2 tm r2,r1 tm ir2,r1 tm r1,im b 8 ld r1, x, r2 b 9 rl r1 rl ir1 ld r2, x, r1 l a cp r1,r2 cp r1,ir2 cp r2,r1 cp ir2,r1 cp r1,im ldc r1, irr2, xl e b clr r1 clr ir1 xor r1,r2 xor r1,ir2 xor r2,r1 xor ir2,r1 xor r1,im ldc r2, irr2, xl c rrc r1 rrc ir1 ldc r1,irr2 ld r1, ir2 h d sra r1 sra ir1 ldc r2,irr1 ld ir1,im ld ir1, r2 e e rr r1 rr ir1 ldcd r1,irr2 ldci r1,irr2 ld r2,r1 ld r2,ir1 ld r1,im ldc r1, irr2, xs x f call irr1 ld ir2,r1 call da1 ldc r2, irr1, xs
sam88rcri instruction set s3c9454b/f945 4b 6- 8 table 6-5. opcode quick reference (continued) opcode map lower nibble (hex) ? 8 9 a b c d e f u 0 ld r1,r2 ld r2,r1 jr cc,ra ld r1,im jp cc,da inc r1 p 1 p 2 e 3 r 4 5 n 6 idle i 7 stop b 8 di b 9 ei l a ret e b iret c rcf h d scf e e ccf x f ld r1,r2 ld r2,r1 jr cc,ra ld r1,im jp cc,da inc r1 nop
s3c9454b/f9454b sam88rcri instruction set 6- 9 condition codes the opcode of a conditional jump always contains a 4-bit field called the condition code (cc). this specifies under which conditions it is to execute the jump. for example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. condition codes are listed in table 6-6. the carry (c), zero (z), sign (s), and overflow (v) flags are used to control the operation of conditional jump instructions. table 6-6. condition codes binary mnemonic description flags set 0000 f always false ? 1000 t always true ? 0111 (1) c carry c = 1 1111 (1) nc no carry c = 0 0110 (1) z zero z = 1 1110 (1) nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 (1) eq equal z = 1 1110 (1) ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than (z or (s xor v)) = 0 0010 le less than or equal (z or (s xor v)) = 1 1111 (1) uge unsigned greater than or equal c = 0 0111 (1) ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 notes: 1. it indicates condition codes that are related to two different mnemonics but which test the same flag. for example, z and eq are both true if the zero flag (z) is set, but after an add instruction, z would probably be used; after a cp instruction, however, eq would probably be used. 2. for operations involving unsigned numbers, the special condition codes uge, ult, ugt, and ule must be used.
sam88rcri instruction set s3c9454b/f945 4b 6- 10 instruction descriptions this section contains detailed information and programming examples for each instruction in the sam87ri instruction set. information is arranged in a consistent format for improved readability and for fast referencing. the following information is included in each instruction description: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? shorthand notation of the instruction's operation ? textual description of the instruction's effect ? specific flag settings affected by the instruction ? detailed description of the instruction's format, execution time, and addressing mode(s) ? programming example(s) explaining how to use the instruction
s3c9454b/f9454b sam88rcri instruction set 6- 11 adc ? add with carry adc dst,src operation: dst ? dst + src + c the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. in multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 r r 6 15 r ir opc dst src 3 6 16 r im examples: given: r1 = 10h, r2 = 03h, c flag = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: adc r1,r2 ? r1 = 14h, r2 = 03h adc r1,@r2 ? r1 = 1bh, r2 = 03h adc 01h,02h ? register 01h = 24h, register 02h = 03h adc 01h,@02h ? register 01h = 2bh, register 02h = 03h adc 01h,#11h ? register 01h = 32h in the first example, destination register r1 contains the value 10h, the carry flag is set to "1", and the source working register r2 contains the value 03h. the statement "adc r1,r2" adds 03h and the carry flag value ("1") to the destination value 10h, leaving 14h in register r1.
sam88rcri instruction set s3c9454b/f945 4b 6- 12 add ? add add dst,src operation: dst ? dst + src the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 r r 6 05 r ir opc dst src 3 6 06 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: add r1,r2 ? r1 = 15h, r2 = 03h add r1,@r2 ? r1 = 1ch, r2 = 03h add 01h,02h ? register 01h = 24h, register 02h = 03h add 01h,@02h ? register 01h = 2bh, register 02h = 03h add 01h,#25h ? register 01h = 46h in the first example, destination working register r1 contains 12h and the source working register r2 contains 03h. the statement "add r1,r2" adds 03h to 12h, leaving the value 15h in register r1.
s3c9454b/f9454b sam88rcri instruction set 6- 13 and ? logical and and dst,src operation: dst ? dst and src the source operand is logically anded with the destination operand. the result is stored in the destination. the and operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. the contents of the source are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 r r 6 55 r ir opc dst src 3 6 56 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: and r1,r2 ? r1 = 02h, r2 = 03h and r1,@r2 ? r1 = 02h, r2 = 03h and 01h,02h ? register 01h = 01h, register 02h = 03h and 01h,@02h ? register 01h = 00h, register 02h = 03h and 01h,#25h ? register 01h = 21h in the first example, destination working register r1 contains the value 12h and the source working register r2 contains 03h. the statement "and r1,r2" logically ands the source operand 03h with the destination operand value 12h, leaving the value 02h in register r1.
sam88rcri instruction set s3c9454b/f945 4b 6- 14 call ? call procedure call dst operation: sp ? sp ? 1 @sp ? pcl sp ? sp ?1 @sp ? pch pc ? dst the current contents of the program counter are pushed onto the top of the stack. the program counter value used is the address of the first instruction following the call instruction. the specified destination address is then loaded into the program counter and points to the first instruction of a procedure. at the end of the procedure the return instruction (ret) can be used to return to the original program flow. ret pops the top of the stack back into the program counter. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 3 14 f6 da opc dst 2 12 f4 irr examples: given: r0 = 15h, r1 = 21h, pc = 1a47h, and sp = 0b2h: call 1521h ? sp = 0b0h (memory locations 00h = 1ah, 01h = 4ah, where 4ah is the address that follows the instruction.) call @rr0 ? sp = 0b0h (00h = 1ah, 01h = 49h) in the first example, if the program counter value is 1a47h and the stack pointer contains the value 0b2h, the statement "call 1521h" pushes the current pc value onto the top of the stack. the stack pointer now points to memory location 00h. the pc is then loaded with the value 1521h, the address of the first instruction in the program sequence to be executed. if the contents of the program counter and stack pointer are the same as in the first example, the statement "call @rr0" produces the same result except that the 49h is stored in stack location 01h (because the two-byte instruction format was used). the pc is then loaded with the value 1521h, the address of the first instruction in the program sequence to be executed.
s3c9454b/f9454b sam88rcri instruction set 6- 15 ccf ? complement carry flag ccf operation: c ? not c the carry flag (c) is complemented. if c = "1", the value of the carry flag is changed to logic zero; if c = "0", the value of the carry flag is changed to logic one. flags: c: complemented. no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 ef example: given: the carry flag = "0": ccf if the carry flag = "0", the ccf instruction complements it in the flags register (0d5h), changing its value from logic zero to logic one.
sam88rcri instruction set s3c9454b/f945 4b 6- 16 clr ? clear clr dst operation: dst ? "0" the destination location is cleared to "0". flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 b0 r 4 b1 ir examples: given: register 00h = 4fh, register 01h = 02h, and register 02h = 5eh: clr 00h ? register 00h = 00h clr @01h ? register 01h = 02h, register 02h = 00h in register (r) addressing mode, the statement "clr 00h" clears the destination register 00h value to 00h. in the second example, the statement "clr @01h" uses indirect register (ir) addressing mode to clear the 02h register value to 00h.
s3c9454b/f9454b sam88rcri instruction set 6- 17 com ? complement com dst operation: dst ? not dst the contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 60 r 4 61 ir examples: given: r1 = 07h and register 07h = 0f1h: com r1 ? r1 = 0f8h com @r1 ? r1 = 07h, register 07h = 0eh in the first example, destination working register r1 contains the value 07h (00000111b). the statement "com r1" complements all the bits in r1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0f8h (11111000b). in the second example, indirect register (ir) addressing mode is used to complement the value of destination register 07h (11110001b), leaving the new value 0eh (00001110b).
sam88rcri instruction set s3c9454b/f945 4b 6- 18 cp ? compare cp dst,src operation: dst ? src the source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. the contents of both operands are unaffected by the comparison. flags: c: set if a "borrow" occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 a2 r r 6 a3 r lr opc src dst 3 6 a4 r r 6 a5 r ir opc dst src 3 6 a6 r im examples: 1. given: r1 = 02h and r2 = 03h: cp r1,r2 ? set the c and s flags destination working register r1 contains the value 02h and source register r2 contains the value 03h. the statement "cp r1,r2" subtracts the r2 value (source/subtrahend) from the r1 value (destination/minuend). because a "borrow" occurs and the difference is negative, c and s are "1". 2. given: r1 = 05h and r2 = 0ah: cp r1,r2 jp uge,skip inc r1 skip ld r3,r1 in this example, destination working register r1 contains the value 05h which is less than the contents of the source working register r2 (0ah). the statement "cp r1,r2" generates c = "1" and the jp instruction does not jump to the skip location. after the statement "ld r3,r1" executes, the value 06h remains in working register r3.
s3c9454b/f9454b sam88rcri instruction set 6- 19 dec ? decrement dec dst operation: dst ? dst ? 1 the contents of the destination operand are decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, dst value is ? 128 (80h) and result value is + 127 (7fh); cleared otherwise. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 00 r 4 01 ir examples: given: r1 = 03h and register 03h = 10h: dec r1 ? r1 = 02h dec @r1 ? register 03h = 0fh in the first example, if working register r1 contains the value 03h, the statement "dec r1" decrements the hexadecimal value by one, leaving the value 02h. in the second example, the statement "dec @r1" decrements the value 10h contained in the destination register 03h by one, leaving the value 0fh.
sam88rcri instruction set s3c9454b/f945 4b 6- 20 di ? disable interrupts di operation: sym (2) ? 0 bit zero of the system mode register, sym.2, is cleared to "0", globally disabling all interrupt processing. interrupt requests will continue to set their respective interrupt pending bits, but the cpu will not service them while interrupt processing is disabled. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 8f example: given: sym = 04h: di if the value of the sym register is 04h, the statement "di" leaves the new value 00h in the register and clears sym.2 to "0", disabling interrupt processing.
s3c9454b/f9454b sam88rcri instruction set 6- 21 ei ? enable interrupts ei operation: sym (2) ? 1 an ei instruction sets bit 2 of the system mode register, sym.2 to "1". this allows interrupts to be serviced as they occur. if an interrupt's pending bit was set while interrupt processing was disabled (by executing a di instruction), it will be serviced when you execute the ei instruction. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 9f example: given: sym = 00h: ei if the sym register contains the value 00h, that is, if interrupts are currently disabled, the statement "ei" sets the sym register to 04h, enabling all interrupts. (sym.2 is the enable bit for global interrupt processing.)
sam88rcri instruction set s3c9454b/f945 4b 6- 22 idle ? idle operation idle operation: the idle instruction stops the cpu clock while allowing system clock oscillation to continue. idle mode can be released by an interrupt request (irq) or an external reset operation. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 6f ? ? example: the instruction idle nop nop nop stops the cpu clock but not the system clock.
s3c9454b/f9454b sam88rcri instruction set 6- 23 inc ? increment inc dst operation: dst ? dst + 1 the contents of the destination operand are incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is dst value is + 127 (7fh) and result is ? 128 (80h); cleared otherwise. format: bytes cycles opcode (hex) addr mode dst dst | opc 1 4 re r r = 0 to f opc dst 2 4 20 r 4 21 ir examples: given: r0 = 1bh, register 00h = 0ch, and register 1bh = 0fh: inc r0 ? r0 = 1ch inc 00h ? register 00h = 0dh inc @r0 ? r0 = 1bh, register 01h = 10h in the first example, if destination working register r0 contains the value 1bh, the statement "inc r0" leaves the value 1ch in that same register. the next example shows the effect an inc instruction has on register 00h, assuming that it contains the value 0ch. in the third example, inc is used in indirect register (ir) addressing mode to increment the value of register 1bh from 0fh to 10h.
sam88rcri instruction set s3c9454b/f945 4b 6- 24 iret ? interrupt return iret iret operation: flags ? @sp sp ? sp + 1 pc ? @sp sp ? sp + 2 sym(2) ? 1 this instruction is used at the end of an interrupt service routine. it restores the flag register and the program counter. it also re-enables global interrupts. flags: all flags are restored to their original settings (that is, the settings before the interrupt occurred). format: iret (normal) bytes cycles opcode (hex) opc 1 10 bf 12
s3c9454b/f9454b sam88rcri instruction set 6- 25 jp ? jump jp cc,dst (conditional) jp dst (unconditional) operation: if cc is true, pc ? dst the conditional jump instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the jp instruction is executed. the unconditional jp simply replaces the contents of the pc with the contents of the specified register pair. control then passes to the statement addressed by the pc. flags: no flags are affected. format: (1) (2) bytes cycles opcode (hex) addr mode dst cc | opc dst 3 8 ccd da cc = 0 to f opc dst 2 8 30 irr notes : 1. the 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. in the first byte of the three-byte instruction format (conditional jump), the condition code and the op code are both four bits. examples: given: the carry flag (c) = "1", register 00 = 01h, and register 01 = 20h: jp c,label_w ? label_w = 1000h, pc = 1000h jp @00h ? pc = 0120h the first example shows a conditional jp. assuming that the carry flag is set to "1", the statement "jp c,label_w" replaces the contents of the pc with the value 1000h and transfers control to that location. had the carry flag not been set, control would then have passed to the statement immediately following the jp instruction. the second example shows an unconditional jp. the statement "jp @00" replaces the contents of the pc with the contents of the register pair 00h and 01h, leaving the value 0120h.
sam88rcri instruction set s3c9454b/f945 4b 6- 26 jr ? jump relative jr cc,dst operation: if cc is true, pc ? pc + dst if the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the jr instruction is executed (see list of condition codes). the range of the relative address is + 127, ? 128, and the original value of the program counter is taken to be the address of the first instruction byte following the jr statement. flags: no flags are affected. format: (note) bytes cycles opcode (hex) addr mode dst cc | opc dst 2 6 ccb ra cc = 0 to f note : in the first byte of the two-byte instruction format, the condition code and the op code are each four bits. example: given: the carry flag = "1" and label_x = 1ff7h: jr c,label_x ? pc = 1ff7h if the carry flag is set (that is, if the condition code is true), the statement "jr c,label_x" will pass control to the statement whose address is now in the pc. otherwise, the program instruction following the jr would be executed.
s3c9454b/f9454b sam88rcri instruction set 6- 27 ld ? load ld dst,src operation: dst ? src the contents of the source are loaded into the destination. the source's contents are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src dst | opc src 2 4 rc r im 4 r8 r r src | opc dst 2 4 r9 r r r = 0 to f opc dst | src 2 4 c7 r lr 4 d7 ir r opc src dst 3 6 e4 r r 6 e5 r ir opc dst src 3 6 e6 r im 6 d6 ir im opc src dst 3 6 f5 ir r opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r
sam88rcri instruction set s3c9454b/f945 4b 6- 28 ld ? load ld (continued) examples: given: r0 = 01h, r1 = 0ah, register 00h = 01h, register 01h = 20h, register 02h = 02h, loop = 30h, and register 3ah = 0ffh: ld r0,#10h ? r0 = 10h ld r0,01h ? r0 = 20h, register 01h = 20h ld 01h,r0 ? register 01h = 01h, r0 = 01h ld r1,@r0 ? r1 = 20h, r0 = 01h ld @r0,r1 ? r0 = 01h, r1 = 0ah, register 01h = 0ah ld 00h,01h ? register 00h = 20h, register 01h = 20h ld 02h,@00h ? register 02h = 20h, register 00h = 01h ld 00h,#0ah ? register 00h = 0ah ld @00h,#10h ? register 00h = 01h, register 01h = 10h ld @00h,02h ? register 00h = 01h, register 01h = 02, register 02h = 02h ld r0,#loop[r1] ? r0 = 0ffh, r1 = 0ah ld #loop[r0],r1 ? register 31h = 0ah, r0 = 01h, r1 = 0ah
s3c9454b/f9454b sam88rcri instruction set 6- 29 ldc/lde ? load memory ldc/lde dst,src operation: dst ? src this instruction loads a byte from program or data memory into a working register or vice-versa. the source values are unaffected. ldc refers to program memory and lde to data memory. the assembler makes "irr" or "rr" values an even number for program memory and odd an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src 1. opc dst | src 2 10 c3 r irr 2. opc src | dst 2 10 d3 irr r 3. opc dst | src xs 3 12 e7 r xs [rr] 4. opc src | dst xs 3 12 f7 xs [rr] r 5. opc dst | src xl l xl h 4 14 a7 r xl [rr] 6. opc src | dst xl l xl h 4 14 b7 xl [rr] r 7. opc dst | 0000 da l da h 4 14 a7 r da 8. opc src | 0000 da l da h 4 14 b7 da r 9. opc dst | 0001 da l da h 4 14 a7 r da 10. opc src | 0001 da l da h 4 14 b7 da r notes : 1. the source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0?1. 2. for formats 3 and 4, the destination address "xs [rr]" and the source address "xs [rr]" are each one byte. 3. for formats 5 and 6, the destination address "xl [rr]" and the source address "xl [rr]" are each two bytes. 4. the da and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.
sam88rcri instruction set s3c9454b/f945 4b 6- 30 ldc/lde ? load memory ldc/lde (continued) examples: given: r0 = 11h, r1 = 34h, r2 = 01h, r3 = 04h, r4 = 00h, r5 = 60h; program memory locations 0061 = aah, 0103h = 4fh, 0104h = 1a, 0105h = 6dh, and 1104h = 88h. external data memory locations 0061h = bbh, 0103h = 5fh, 0104h = 2ah, 0105h = 7dh, and 1104h = 98h: ldc r0,@rr2 ; r0 ? contents of program memory location 0104h ; r0 = 1ah, r2 = 01h, r3 = 04h lde r0,@rr2 ; r0 ? contents of external data memory location 0104h ; r0 = 2ah, r2 = 01h, r3 = 04h ldc (note) @rr2,r0 ; 11h (contents of r0) is loaded into program memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change lde @rr2,r0 ; 11h (contents of r0) is loaded into external data memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change ldc r0,#01h[rr4] ; r0 ? contents of program memory location 0061h ; (01h + rr4), ; r0 = aah, r2 = 00h, r3 = 60h lde r0,#01h[rr4] ; r0 ? contents of external data memory location 0061h ; (01h + rr4), r0 = bbh, r4 = 00h, r5 = 60h ldc (note) #01h[rr4],r0 ; 11h (contents of r0) is loaded into program memory location ; 0061h (01h + 0060h) lde #01h[rr4],r0 ; 11h (contents of r0) is loaded into external data memory ; location 0061h (01h + 0060h) ldc r0,#1000h[rr2] ; r0 ? contents of program memory location 1104h ; (1000h + 0104h), r0 = 88h, r2 = 01h, r3 = 04h lde r0,#1000h[rr2] ; r0 ? contents of external data memory location 1104h ; (1000h + 0104h), r0 = 98h, r2 = 01h, r3 = 04h ldc r0,1104h ; r0 ? contents of program memory location 1104h, r0 = 88h lde r0,1104h ; r0 ? contents of external data memory location 1104h, ; r0 = 98h ldc (note) 1105h,r0 ; 11h (contents of r0) is loaded into program memory location ; 1105h, (1105h) ? 11h lde 11 05h,r0 ; 11h (contents of r0) is loaded into external data memory ; location 1105h, (1105h) ? 11h note : these instructions are not supported by masked rom type devices.
s3c9454b/f9454b sam88rcri instruction set 6- 31 ldcd/lded ? load memory and decrement ldcd/lded dst,src operation: dst ? src rr ? rr ? 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then decremented. the contents of the source are unaffected. ldcd references program memory and lded references external data memory. the assembler makes "irr" an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e2 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory location 1033h = 0cdh, and external data memory location 1033h = 0ddh: ldcd r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is decremented by one ; r8 = 0cdh, r6 = 10h, r7 = 32h (rr6 ? rr6 ? 1) lded r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is decremented by one (rr6 ? rr6 ? 1) ; r8 = 0ddh, r6 = 10h, r7 = 32h
sam88rcri instruction set s3c9454b/f945 4b 6- 32 ldci/ldei ? load memory and increment ldci/ldei dst,src operation: dst ? src rr ? rr + 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then incremented automatically. the contents of the source are unaffected. ldci refers to program memory and ldei refers to exte rnal data memory. the assembler makes "irr" even for program memory and odd for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e3 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory locations 1033h = 0cdh and 1034h = 0c5h; external data memory locations 1033h = 0ddh and 1034h = 0d5h: ldci r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is incremente d by one (rr6 ? rr6 + 1) ; r8 = 0cdh, r6 = 10h, r7 = 34h ldei r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 ? rr6 + 1) ; r8 = 0ddh, r6 = 10h, r7 = 34h
s3c9454b/f9454b sam88rcri instruction set 6- 33 nop ? no operation nop operation: no action is performed when the cpu executes this instruction. typically, one or more nops are executed in sequence in order to effect a timing delay of variable duration. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 ff example: when the instruction nop is encountered in a program, no operation occurs. instead, there is a delay in instruction execution time.
sam88rcri instruction set s3c9454b/f945 4b 6- 34 or ? logical or or dst,src operation: dst ? dst or src the source operand is logically ored with the destination operand and the result is stored in the destination. the contents of the source are unaffected. the or operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 r r 6 45 r ir opc dst src 3 6 46 r im examples: given: r0 = 15h, r1 = 2ah, r2 = 01h, register 00h = 08h, register 01h = 37h, and register 08h = 8ah: or r0,r1 ? r0 = 3fh, r1 = 2ah or r0,@r2 ? r0 = 37h, r2 = 01h, register 01h = 37h or 00h,01h ? register 00h = 3fh, register 01h = 37h or 01h,@00h ? register 00h = 08h, register 01h = 0bfh or 00h,#02h ? register 00h = 0ah in the first example, if working register r0 contains the value 15h and register r1 the value 2ah, the statement "or r0,r1" logical-ors the r0 and r1 register contents and stores the result (3fh) in destination register r0. the other examples show the use of the logical or instruction with the various addressing modes and formats.
s3c9454b/f9454b sam88rcri instruction set 6- 35 pop ? pop from stack pop dst operation: dst ? @sp sp ? sp + 1 the contents of the location addressed by the stack pointer are loaded into the destination. the stack pointer is then incremented by one. flags: no flags affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 50 r 8 51 ir examples: given: register 00h = 01h, register 01h = 1bh, sp (0d9h) = 0bbh, and stack register 0bbh = 55h: pop 00h ? register 00h = 55h, sp = 0bch pop @00h ? register 00h = 01h, register 01h = 55h, sp = 0bch in the first example, general register 00h contains the value 01h. the statement "pop 00h" loads the contents of location 0bbh (55h) into destination register 00h and then increments the stack pointer by one. register 00h then contains the value 55h and the sp points to location 0bch.
sam88rcri instruction set s3c9454b/f945 4b 6- 36 push ? push to stack push src operation: sp ? sp ? 1 @sp ? src a push instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. the operation then adds the new value to the top of the stack. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc src 2 8 70 r 8 71 ir examples: given: register 40h = 4fh, register 4fh = 0aah, sp = 0c0h: push 40h ? register 40h = 4fh, stack register 0bfh = 4fh, sp = 0bfh push @40h ? register 40h = 4fh, register 4fh = 0aah, stack register 0bfh = 0aah, sp = 0bfh in the first example, if the stack pointer contains the value 0c0h, and general register 40h the value 4fh, the statement "push 40h" decrements the stack pointer from 0c0 to 0bfh. it then loads the contents of register 40h into location 0bfh. register 0bfh then contains the value 4fh and sp points to location 0bfh.
s3c9454b/f9454b sam88rcri instruction set 6- 37 rcf ? reset carry flag rcf rcf operation: c ? 0 the carry flag is cleared to logic zero, regardless of its previous value. flags: c: cleared to "0". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 cf example: given: c = "1" or "0": the instruction rcf clears the carry flag (c) to logic zero.
sam88rcri instruction set s3c9454b/f945 4b 6- 38 ret ? return ret operation: pc ? @sp sp ? sp + 2 the ret instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a call instruction. the contents of the location addressed by the stack pointer are popped into the program counter. the next statement that is executed is the one that is addressed by the new program counter value. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 8 af 10 example: given: sp = 0bch, (sp) = 101ah, and pc = 1234: ret ? pc = 101ah, sp = 0beh the statement "ret" pops the contents of stack pointer location 0bch (10h) into the high byte of the program counter. the stack pointer then pops the value in location 0bdh (1ah) into the pc's low byte and the instruction at location 101ah is executed. the stack pointer now points to memory location 0beh.
s3c9454b/f9454b sam88rcri instruction set 6- 39 rl ? rotate left rl dst operation: c ? dst (7) dst (0) ? dst (7) dst (n + 1) ? dst (n), n = 0?6 the contents of the destination operand are rotated left one bit position. the initial value of bit 7 is moved to the bit zero (lsb) position and also replaces the carry flag. c 7 0 flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 90 r 4 91 ir examples: given: register 00h = 0aah, register 01h = 02h and register 02h = 17h: rl 00h ? register 00h = 55h, c = "1" rl @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h contains the value 0aah (10101010b), the statement "rl 00h" rotates the 0aah value left one bit position, leaving the new value 55h (01010101b) and setting the carry and overflow flags.
sam88rcri instruction set s3c9454b/f945 4b 6- 40 rlc ? rotate left through carry rlc dst operation: dst (0) ? c c ? dst (7) dst (n + 1) ? dst (n), n = 0?6 the contents of the destination operand with the carry flag are rotated left one bit position. the initial value of bit 7 replaces the carry flag (c); the initial value of the carry flag replaces bit zero. c 7 0 flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 10 r 4 11 ir examples: given: register 00h = 0aah, register 01h = 02h, and register 02h = 17h, c = "0": rlc 00h ? register 00h = 54h, c = "1" rlc @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h has the value 0aah (10101010b), the statement "rlc 00h" rotates 0aah one bit position to the left. the initial value of bit 7 sets the carry flag and the initial value of the c flag replaces bit zero of register 00h, leaving the value 55h (01010101b). the msb of register 00h resets the carry flag to "1" and sets the overflow flag.
s3c9454b/f9454b sam88rcri instruction set 6- 41 rr ? rotate right rr dst operation: c ? dst (0) dst (7) ? dst (0) dst (n) ? dst (n + 1), n = 0?6 the contents of the destination operand are rotated right one bit position. the initial value of bit zero (lsb) is moved to bit 7 (msb) and also replaces the carry flag (c). c 7 0 flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 e0 r 4 e1 ir examples: given: register 00h = 31h, register 01h = 02h, and register 02h = 17h: rr 00h ? register 00h = 98h, c = "1" rr @01h ? register 01h = 02h, register 02h = 8bh, c = "1" in the first example, if general register 00h contains the value 31h (00110001b), the statement "rr 00h" rotates this value one bit position to the right. the initial value of bit zero is moved to bit 7, leaving the new value 98h (10011000b) in the destination register. the initial bit zero also resets the c flag to "1" and the sign flag and overflow flag are also set to "1".
sam88rcri instruction set s3c9454b/f945 4b 6- 42 rrc ? rotate right through carry rrc dst operation: dst (7) ? c c ? dst (0) dst (n) ? dst (n + 1), n = 0?6 the contents of the destination operand and the carry flag are rotated right one bit position. the initial value of bit zero (lsb) replaces the carry flag; the initial value of the carry flag replaces bit 7 (msb). c 7 0 flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0" cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 c0 r 4 c1 ir examples: given: register 00h = 55h, register 01h = 02h, register 02h = 17h, and c = "0": rrc 00h ? register 00h = 2ah, c = "1" rrc @01h ? register 01h = 02h, register 02h = 0bh, c = "1" in the first example, if general register 00h contains the value 55h (01010101b), the statement "rrc 00h" rotates this value one bit position to the right. the initial value of bit zero ("1") replaces the carry flag and the initial value of the c flag ("1") replaces bit 7. this leaves the new value 2ah (00101010b) in destination register 00h. the sign flag and overflow flag are both cleared to "0".
s3c9454b/f9454b sam88rcri instruction set 6- 43 sbc ? subtract with carry sbc dst,src operation: dst ? dst ? src ? c the source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's-complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. flags: c: set if a borrow occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 r r 6 35 r ir opc dst src 3 6 36 r im examples: given: r1 = 10h, r2 = 03h, c = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: sbc r1,r2 ? r1 = 0ch, r2 = 03h sbc r1,@r2 ? r1 = 05h, r2 = 03h, register 03h = 0ah sbc 01h,02h ? register 01h = 1ch, register 02h = 03h sbc 01h,@02h ? register 01h = 15h,register 02h = 03h, register 03h = 0ah sbc 01h,#8ah ? register 01h = 95h; c, s, and v = "1" in the first example, if working register r1 contains the value 10h and register r2 the value 03h, the statement "sbc r1,r2" subtracts the source value (03h) and the c flag value ("1") from the destination (10h) and then stores the result (0ch) in register r1.
sam88rcri instruction set s3c9454b/f945 4b 6- 44 scf ? set carry flag scf operation: c ? 1 the carry flag (c) is set to logic one, regardless of its previous value. flags: c: set to "1". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 df example: the statement scf sets the carry flag to logic one.
s3c9454b/f9454b sam88rcri instruction set 6- 45 sra ? shift right arithmetic sra dst operation: dst (7) ? dst (7) c ? dst (0) dst (n) ? dst (n + 1), n = 0?6 an arithmetic shift-right of one bit position is performed on the destination operand. bit zero (the lsb) replaces the carry flag. the value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. c 7 0 6 flags: c: set if the bit shifted from the lsb position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: always cleared to "0". format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 d0 r 4 d1 ir examples: given: register 00h = 9ah, register 02h = 03h, register 03h = 0bch, and c = "1": sra 00h ? register 00h = 0cd, c = "0" sra @02h ? register 02h = 03h, register 03h = 0deh, c = "0" in the first example, if general register 00h contains the value 9ah (10011010b), the statement "sra 00h" shifts the bit values in register 00h right one bit position. bit zero ("0") clears the c flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). this leaves the value 0cdh (11001101b) in destination register 00h.
sam88rcri instruction set s3c9454b/f945 4b 6- 46 stop ? stop operation stop operation: the stop instruction stops the both the cpu clock and system clock and causes the microcontroller to enter stop mode. during stop mode, the contents of on-chip cpu registers, peripheral registers, and i/o port control and data registers are retained. stop mode can be released by an external reset operation or external interrupt input. for the reset operation, the reset pin must be held to low level until the required oscillation stabilization interval has elapsed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 7f ? ? example: the statement ld stopcon, #0a5h stop nop nop nop halts all microcontroller operations. when stopcon register is not #0a5h value, if you use stop instruction, pc is changed to reset address.
s3c9454b/f9454b sam88rcri instruction set 6- 47 sub ? subtract sub dst,src operation: dst ? dst ? src the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's complement of the source operand to the destination operand. flags: c: set if a "borrow" occurred; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 r r 6 25 r ir opc dst src 3 6 26 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: sub r1,r2 ? r1 = 0fh, r2 = 03h sub r1,@r2 ? r1 = 08h, r2 = 03h sub 01h,02h ? register 01h = 1eh, register 02h = 03h sub 01h,@02h ? register 01h = 17h, register 02h = 03h sub 01h,#90h ? register 01h = 91h; c, s, and v = "1" sub 01h,#65h ? register 01h = 0bch; c and s = "1", v = "0" in the first example, if working register r1 contains the value 12h and if register r2 contains the value 03h, the statement "sub r1,r2" subtracts the source value (03h) from the destination value (12h) and stores the result (0fh) in destination register r1.
sam88rcri instruction set s3c9454b/f945 4b 6- 48 tcm ? test complement under mask tcm dst,src operation: (not dst) and src this instruction tests selected bits in the destination operand for a logic one value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). the tcm statement complements the destination operand, which is then anded with the source mask. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 r r 6 65 r ir opc dst src 3 6 66 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 12h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tcm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "1" tcm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tcm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "1" tcm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "1" tcm 00h,#34 ? register 00h = 2bh, z = "0" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tcm r0,r1" tests bit one in the destination register for a "1" value. because the mask value corresponds to the test bit, the z flag is set to logic one and can be tested to determine the result of the tcm operation.
s3c9454b/f9454b sam88rcri instruction set 6- 49 tm ? test under mask tm dst,src operation: dst and src this instruction tests selected bits in the destination operand for a logic zero value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is anded with the destination operand. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 r r 6 75 r ir opc dst src 3 6 76 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "0" tm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "0" tm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "0" tm 00h,#54h ? register 00h = 2bh, z = "1" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tm r0,r1" tests bit one in the destination register for a "0" value. because the mask value does not match the test bit, the z flag is cleared to logic zero and can be tested to determine the result of the tm operation.
sam88rcri instruction set s3c9454b/f945 4b 6- 50 xor ? logical exclusive or xor dst,src operation: dst ? dst xor src the source operand is logically exclusive-ored with the destination operand and the result is stored in the destination. the exclusive-or operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 b2 r r 6 b3 r lr opc src dst 3 6 b4 r r 6 b5 r ir opc dst src 3 6 b6 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: xor r0,r1 ? r0 = 0c5h, r1 = 02h xor r0,@r1 ? r0 = 0e4h, r1 = 02h, register 02h = 23h xor 00h,01h ? register 00h = 29h, register 01h = 02h xor 00h,@01h ? register 00h = 08h, register 01h = 02h, register 02h = 23h xor 00h,#54h ? register 00h = 7fh in the first example, if working register r0 contains the value 0c7h and if register r1 contains the value 02h, the statement "xor r0,r1" logically exclusive-ors the r1 value with the r0 value and stores the result (0c5h) in the destination register r0.
s3c9454b/f9454b clock circuit 7- 1 7 clock circuit overview by smart option (3fh.1 ?.0 in rom), user can select internal rc oscillator or external oscillator. in using internal oscillator, x in (p1.0), x out (p1.1) can be used by normal i/o pins. an internal rc oscillator source provides a typical 3.2 mhz or 0.5 mhz (in v dd = 5 v) depending on smart option. an external rc oscillation source provides a typical 4 mhz clock for s3c9454b/f9454b. an internal capacitor supports the rc oscillator circuit. an external crystal or ceramic oscillation source provides a maximum 10 mhz clock. the x in and x out pins connect the oscillation source to the on-chip clock circuit. simplified external rc oscillator and crystal/ceramic oscillator circuits are shown in figures 7-1 and 7-2. when you use external oscillator, p1.0, p1.1 must be set to output port to prevent current consumption s3c9454b/f9454b x out r figure 7-1. main oscillator circuit (rc oscillator with internal capacitor) s3c9454b/p9454b x out x in c2 c1 figure 7-2. main oscillator circuit (crystal/ceramic oscillator) main oscillator logic to increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator circuit. for this reason, very high resolution waveforms (square signal edges) must be generated in order for the cpu to efficiently process logic operations.
clock circuit s3c9454b/f9454b 7- 2 clock status during power-down modes the two power-down modes, stop mode and idle mode, affect clock oscillation as follows: ? in stop mode, the main oscillator "freezes", halting the cpu and peripherals. the contents of the register file and current system register values are retained. stop mode is released, and the oscillator started, by a reset operation or by an external interrupt with rc-delay noise filter (for s3c9454b/f9454b, int0?int1). ? in idle mode, the internal clock signal is gated off to the cpu, but not to interrupt control and the timer. the current cpu status is preserved, including stack pointer, program counter, and flags. data in the register file is retained. idle mode is released by a reset or by an interrupt (external or internally-generated). system clock control register (clkcon) the system clock control register, clkcon, is located in location d4h. it is read/write addressable and has the following functions: ? oscillator irq wake-up function enable/disable (clkcon.7) ? oscillator frequency divide-by value: non-divided, 2, 8, or 16 (clkcon.4 and clkcon.3) the clkcon register controls whether or not an external interrupt can be used to trigger a stop mode release (this is called the "irq wake-up" function). the irq wake-up enable bit is clkcon.7. after a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the f osc /16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed to f osc , f osc /2 or f osc /8. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb system clock control register (clkcon) d4h, r/w divide-by selection bits for cpu clock frequency: 00 = fosc/16 01 = fosc/8 10 = fosc/2 11 = fosc (non-divided) oscillator irq wake-up enable bit: 0 = enable irq for main system oscillator wake-up function in power mode. 1 = disable irq for main system oscillator wake-up function in power down mode. not used for s3c9454b/f9454b not used for s3c9454b/f9454b figure 7-3. system clock control register (clkcon)
s3c9454b/f9454b clock circuit 7- 3 mux selected osc noise filter oscillator wake-up oscillator stop clkcon.7 int pin clkcon.4-.3 1/2 p2conh.6-.4 1/16 m u x stop instruction cpu clock internal rc oscillator (3.2 mhz) internal rc oscillator (0.5 mhz) external crystal/ ceramic oscillator note: an external interrupt (with rc-delay noise filter) can be used to release stop mode and "wake-up" the main oscillator. in the s3c9454b/f9454b, the int0-int1 external interrupts are of this type. p2.6/clo smart option (3f.1-0 in rom) 1/8 external rc oscillator figure 7-4. system clock circuit diagram
clock circuit s3c9454b/f9454b 7- 4 notes
s39454b/f9454b reset and power-down 8- 1 8 reset and power-down system reset overview by smart option (3eh.7 in rom), user can select internal reset (lvr) or external reset. in using internal reset (lvr), nreset pin (p1.2) can be used by normal i/o pin. the s3c9454b/f9454b can be reset in four ways: ? by external power-on-reset ? by the external nreset input pin pulled low ? by the digital watchdog peripheral timing out ? by low voltage reset (lvr) during a external power-on reset, the voltage at v dd is high level and the nreset pin is forced to low level. the nreset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this brings the s3c9454b/f9454b into a known operating status. to ensure correct start-up, the user should take care that nreset signal is not released before the v dd level is sufficient to allow mcu operation at the chosen frequency. the nreset pin must be held to low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal cpu clock oscillation to stabilize. the minimum required oscillation stabilization time for a reset is approximately 6.55 ms (@ 2 16 / f osc , f osc = 10 mhz). when a reset occurs during normal operation (with both v dd and nreset at high level), the signal at the nreset pin is forced low and the reset operation starts. all system and peripheral control registers are then set to their default hardware reset values (see table 8-1). the mcu provides a watchdog timer function in order to ensure graceful recovery from software malfunction. if watchdog timer is not refreshed before an end-of-counter condition (overflow) is reached, the internal reset will be activated. the on-chip low voltage reset, features static reset when supply voltage is below a reference value (typ. 2.3, 3.0, 3.9 v). thanks to this feature, external reset circuit can be removed while keeping the application safety. as long as the supply voltage is below the reference value, there is a internal and static reset. the mcu can start only when the supply voltage rises over the reference value.
reset and power-down s39454b/f9454b 8- 2 note to program the duration of the oscillation stabilization interval, you must make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing "1010b" to the upper nibble of btcon. mcu initialization sequence the following sequence of events occurs during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? ports 0?2 are set to input mode ? peripheral control and data registers are dis abled and reset to their initial values (see table 8-1). ? the program counter is loaded with the rom reset address, 0100h. ? when the programmed oscillation stabilization time interval has elapsed, the address stored in rom location 0100h (and 0101h) is fetched and executed. mux lvr nreset nreset smart option (3eh.7) watchdog nreset internal nreset figure 8-1. reset block diagram nreset input oscillation stabilization wait time (6.55 ms/at 10 mhz) reset operation normal mode or power-down mode idle mode operation mode figure 8-2. timing for s3c9454b/f9454b after reset
s39454b/f9454b reset and power-down 8- 3 power-down modes stop mode stop mode is invoked by the instruction stop (opcode 7fh). in stop mode, the operation of the cpu and all peripherals is halted. that is, the on-chip main oscillator stops and the supply current is reduced to less than 5 m a except that the lvr(low voltage reset) is enable. all system functions are halted when the clock "freezes", but data stored in the internal register file is retained. stop mode can be released in one of two ways: by a nreset signal or by an external interrupt. using reset to release stop mode stop mode is released when the nreset signal is released and returns to high level. all system and peripheral control registers are then reset to their default values and the contents of all data registers are retained. a reset operation automatically selects a slow clock (f osc /16) because clkcon.3 and clkcon.4 are cleared to "00b". after the oscillation stabilization interval has elapsed, the cpu executes the system initialization routine by fetching the 16-bit address stored in rom locations 0100h and 0101h. using an external interrupt to release stop mode external interrupts with an rc-delay noise filter circuit can be used to release stop mode (clock-related external interrupts cannot be used). external interrupts int0-int1 in the s3c9454b/f9454b interrupt structure meet this criteria. note that when stop mode is released by an external interrupt, the current values in system and peripheral control registers are not changed. when you use an interrupt to release stop mode, the clkcon.3 and clkcon.4 register values remain unchanged, and the currently selected clock value is used. if you use an external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must put the appropriate value to btcon register before entering stop mode. the external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed. idle mode idle mode is invoked by the instruction idle (opcode 6fh). in idle mode, cpu operations are halted while select peripherals remain active. during idle mode, the internal clock signal is gated off to the cpu, but not to interrupt logic and timer/counters. port pins retain the mode (input or output) they had at the time idle mode was entered. there are two ways to release idle mode: 1. execute a reset. all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects a slow clock (f osc /16) because clkcon.3 and clkcon.4 are cleared to "00b". if interrupts are masked, a reset is the only way to release idle mode. 2. activate any enabled interrupt, causing idle mode to be released. when you use an interrupt to release idle mode, the clkcon.3 and clkcon.4 register value s remain unchanged, and the currently selected clock value is used. the interrupt is then serviced. following the iret from the service routine, the instruction immediately following the one that initiated idle mode is executed. notes 1. only external interrupts that are not clock-related can be used to release stop mode. to release idle mode, however, any type of interrupt (that is, internal or external) can be used. 2. before enter the stop or idle mode, the adc must be disabled. otherwise, the stop or idle current will be increased significantly.
reset and power-down s39454b/f9454b 8- 4 hardware reset values table 8-1 lists the values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation in normal operating mode. ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an "x" means that the bit value is undefined following a reset. ? a dash ("?") means that the bit is either not used or not mapped. table 8-1. register values after a reset register name mnemonic address & location reset value (bit) address r/w 7 6 5 4 3 2 1 0 timer 0 counter register t0cnt d0h r 0 0 0 0 0 0 0 0 timer 0 data register t0data d1h r/w 1 1 1 1 1 1 1 1 timer 0 control register t0con d2h r/w 0 0 ? ? 0 ? 0 0 location d3h is not mapped clock control register clkcon d4h r/w 0 ? ? 0 0 ? ? ? system flags register flags d5h r/w x x x x ? ? ? ? locations d6h?d8h are not mapped stack pointer register sp d9h r/w x x x x x x x x location dah is not mapped mds special register mdsreg dbh r/w 0 0 0 0 0 0 0 0 basic timer control register btcon dch r/w 0 0 0 0 0 0 0 0 basic timer counter btcnt ddh r 0 0 0 0 0 0 0 0 test mode control register ftstcon deh w ? ? 0 0 0 0 0 0 system mode register sym dfh r/w ? ? ? ? 0 0 0 0 note: ? : not mapped or not used, x: undefined
s39454b/f9454b reset and power-down 8- 5 table 8-1. register values after a reset (continued) register name mnemonic address r/w bit values after reset hex 7 6 5 4 3 2 1 0 port 0 data register p0 e0h r/w 0 0 0 0 0 0 0 0 port 1 data register p1 e1h r/w ? ? ? ? ? 0 0 0 port 2 data register p2 e2h r/w ? 0 0 0 0 0 0 0 locations e3h?e5h are not mapped port 0 control register (high byte) p0conh e6h r/w 0 0 0 0 0 0 0 0 port 0 control register p0con e7h r/w 0 0 0 0 0 0 0 0 port 0 interrupt pending register p0pnd e8h r/w ? ? ? ? 0 0 0 0 port 1 control register p1con e9h r/w 0 0 ? ? 0 0 0 0 port 2 control register (high byte) p2conh eah r/w ? 0 0 0 0 0 0 0 port 2 control register (low byte) p2conl ebh r/w 0 0 0 0 0 0 0 0 locations ech?f1h are not mapped pwm data register pwmdata f2h r/w 0 0 0 0 0 0 0 0 pwm control register pwmcon f3h r/w 0 0 ? 0 0 0 0 0 stop control register stopcon f4h r/w 0 0 0 0 0 0 0 0 locations f5h?f6h are not mapped a/d control register adcon f7h r/w 0 0 0 0 0 0 0 0 a/d converter data register (high) addatah f8h r x x x x x x x x a/d converter data register (low) addatal f9h r 0 0 0 0 0 0 x x locations fah?ffh are not mapped note: ? : not mapped or not used, x: undefined
reset and power-down s39454b/f9454b 8- 6 f programming tip ? sample s3c9454b/f9454b initialization routine ;--------------<< interrupt vector address >> org 0000h vector 00h,int_9454 ; s3c9454b/f9454b has only one interrupt vector ;--------------<< smart option >> org 003ch db 00h ; 003ch, must be initialized to 0 db 00h ; 003dh, must be initialized to 0 db 0e7h ; 003eh, enable lvr (2.3 v) db 03h ; 003fh, internal rc (3.2 mhz in v dd = 5 v ) ;--------------<< initialize system and peripherals >> org 0100h reset: di ; disable interrupt ld btcon,#10100011b ; watch-dog disable ld clkcon,#00011000b ; select non-divided cpu clock ld sp,#0c0h ; stack pointer must be set ld p0conh,#10101010b ; ld p0conl,#10101010b ; p0.0?p0.7 push-pull output ld p1con,#00001010b ; p1.0?p1.1 push-pull output ld p2conh,#01001010b ; ld p2conl,#10101010b ; p2.0?p2.6 push-pull output ;--------------<< timer 0 settings >> ld t0data,#50h ; cpu = 3.2 mhz, interrupt interval = 6.4 msec ld t0con,#01001010b ; f osc /256, timer 0 interrupt enable ;--------------<< clear all data registers from 00h to 5fh >> ld r0,#0 ; ram clear ram_clr: clr @r0 ; inc r0 ; cp r0,#0bfh ; jp ule,ram_clr ;--------------<< initialize other registers >> ei ; enable interrupt
s39454b/f9454b reset and power-down 8- 7 f programming tip ? sample s3c9454b/f9454b initialization routine (continued) ;--------------<< main loop >> main: nop ; start main lo op ld btcon,#02h ; enable watchdog function ; basic counter (btcnt) clear call key_scan ; call led_display ; call job ; jr t,main ; ;--------------<< subroutines >> key_scan: nop ; ret led_display: nop ; ret job: nop ; ret
reset and power-down s39454b/f9454b 8- 8 f programming tip ? sample s3c9454b/f9454b initialization routine (continued) ;--------------<< interrupt service routines >> ; interrupt enable bit and pending bit check int_9454: tm t0con,#00000010b ; timer0 interrupt enable check jr z,next_chk1 ; tm t0con,#00000001b ; if timer0 interrupt was occurred, jp nz,int_timer0 ; t0con.0 bit would be set. next_chk1: tm pwmcom,#00000010b ; pwm overflow interrupt enable check jr z,next_chk2 ; tm p0pnd,#00000001b ; jp nz,pwmovf_int ; next_chk2: tm p0pnd,#00000010b ; int0 interrupt enable check jr z,next_chk3 ; tm p0pnd,#00000001b ; jp nz,int0_int ; next_chk3: tm p0pnd,#00001000b ; int1 interrupt enable check jp z,end_int ; tm p0pnd,#00000100b ; jp nz,int1_int ; iret ; interrupt return end_int ; iret ;--------------< timer0 interrupt service routine > int_timer0: ; and t0con,#1111 0 110b ; pending bit clear iret ; interrupt return ;--------------< pwm overflow interrupt service routine > pwmovf_int: and pwmcon,#11 11 0 110b ; pending bit clear iret ; interrupt return
s39454b/f9454b reset and power-down 8- 9 f programming tip ? sample s3c9454b/f9454b initialization routine (continued) ;--------------< external interrupt0 service routine > int0_int: and p0pnd,#11111110b ; int0 pending bit clear iret ; interrupt return ;--------------< external interrupt1 service routine > int1_int: and p0pnd,#11111011b ; int1 pending bi t clear iret ; interrupt return end ;
reset and power-down s39454b/f9454b 8- 10 notes
s3c9454b/f9454b i/o ports 9- 1 9 i/o ports overview the s3c9454b/f9454b has three i/o ports: with 18 pins total. you access these ports directly by writing or reading port data register addresses. all ports can be configured as led drive. (high current output: typical 10 ma) table 9-1. s3c9454b/f9454b port configuration overview port function description programmability 0 bit-programmable i/o port for schmitt trigger input or push-pull output. pull-up resistors are assignable by software. port 0 pins can also be used as alternative function. (adc input, external interrupt input). bit 1 bit-programmable i/o port for schmitt trigger input or push-pull, open-drain output. pull-up or pull-down resistors are assignable by software. port 1 pins can also oscillator input/output or reset input by smart option. p1.2 is input only. bit 2 bit-programmable i/o port for schmitt trigger input or push-pull, open-drain output. pull-up resistor are assignable by software. port 2 can also be used as alternative function (adc input, clo, t0 clock output) bit
i/o ports s3c9454b/f9454b 9- 2 port data registers table 9-2 gives you an overview of the port data register names, locations, and addressing characteristics. data registers for ports 0-2 have the structure shown in figure 9-1. table 9-2. port data register summary register name mnemonic hex r/w port 0 data register p0 e0h r/w port 1 data register p1 e1h r/w port 2 data register p2 e2h r/w note: a reset operation clears the p0?p2 data register to "00h". .7 .6 .5 .4 .3 .2 .1 .0 lsb msb i/o port n data register (n = 0-2) pn.0 pn.1 pn.2 pn.4 pn.3 pn.5 pn.6 pn.7 figure 9-1. port data register format
s3c9454b/f9454b i/o ports 9- 3 port 0 port 0 is a bit-programmable, general-purpose, i/o ports. you can select normal input or push-pull output mode. in addition, you can configure a pull-up resistor to individual pins using control register settings. it is designed for high-current functions such as led direct drive. part 0 pins can also be used as alternative functions (adc input, external interrupt input and pwm output). two control resisters are used to control port 0: p0conh (e6h) and p0conl (e7h). you access port 0 directly by writing or reading the corresponding port data register, p0 (e0h). v dd in/out output disable (input mode) p0 data v dd pull-up register (50 k w typical) circuit type a input data to adc m u x pull-up enable p0conh pwm mux d0 d1 noise filter external interrupt input note: i/o pins have protection diodes through v dd and v ss . mode input data output input d0 d1 figure 9-2. port 0 circuit diagram
i/o ports s3c9454b/f9454b 9- 4 port 0 control register (high byte) e6h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7-.6] port, p0.7/adc7 configuration bits 0 0 = schmitt trigger input; pull-up enable 0 1 = schmitt trigger input 1 0 = push-pull output 1 1 = a/d converter input (adc7); schmitt trigger input off [.5-.4] port 0, p0.6/adc6/pwm configuration bits 0 0 = schmitt trigger input; pull-up enable 0 1 = alternative function (pwm output) 1 0 = push-pull output 1 1 = a/d converter input (adc6); schmitt trigger input off [.3-.2] port 0, p0.5/adc5 configuration bits 0 0 = schmitt trigger input; pull-up enable 0 1 = schmitt trigger input 1 0 = push-pull output 1 1 = a/d converter input (adc5); schmitt trigger input off [.1-.0] port 0, p0.4/adc4 configuration bits 0 0 = schmitt trigger input; pull-up enable 0 1 = schmitt trigger input 1 0 = push-pull output 1 1 = a/d converter input (adc4); schmitt trigger input off figure 9-3. port 0 control register (p0conh, high byte)
s3c9454b/f9454b i/o ports 9- 5 port 0 control register (low byte) e7h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7-.6] port 0, p0.3/adc3 configuration bits 0 0 = schmitt trigger input 0 1 = schmitt trigger input; pull-up enable 1 0 = push-pull output 1 1 = a/d converter input (adc3); schmitt trigger input off [.5-.4] port 0, p0.2/adc2 configuration bits 0 0 = schmitt trigger input 0 1 = schmitt trigger input; pull-up enable 1 0 = push-pull output 1 1 = a/d converter input (adc2); schmitt trigger input off [.3-.2] port 0, p0.1/adc1/int1 configuration bits 0 0 = schmitt trigger input/falling edge interrupt input 0 1 = schmitt trigger input; pull-up enable/falling edge interrupt input 1 0 = push-pull output 1 1 = a/d converter input (adc1); schmitt trigger input off [.1-.0] port 0, p0.0/adc0/int0 configuration bits 0 0 = schmitt trigger input/falling edge interrupt input 0 1 = schmitt trigger input; pull-up enable/falling edge interrupt input 1 0 = push-pull output 1 1 = a/d converter input (adc0); schmitt trigger input off figure 9-4. port 0 control register (p0conl, low byte)
i/o ports s3c9454b/f9454b 9- 6 port 0 interrupt pending register e8h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7-.4] not used for s3c9454b/f9454b [.3] port 0.1/adc1/int1, interrupt enable bit 0 = int1 falling edge interrupt disable 1 = int1 falling edge interrupt enable [.2] port 0.1/adc1/int1, interrupt pending bit 0 = no interrupt pending (when read) 0 = pending bit clear (when write) 1 = interrupt is pending (when read) 1 = no effect (when write) [.1] port 0.0/adc0/int0, interrupt enable bit 0 = int0 falling edge interrupt disable 1 = int0 falling edge interrupt enable [.0] port 0.0/adc0/int0, interrupt pending bit 0 = no interrupt pending (when read) 0 = pending bit clear (when write) 1 = interrupt is pending (when read) 1 = no effect (when write) figure 9-5. port 0 interrupt pending registers (p0pnd)
s3c9454b/f9454b i/o ports 9- 7 port 1 port 1, is a 3-bit i/o port with individually configurable pins. it can be used for general i/o port (schmitt trigger input mode, push-pull output mode or n-channel open-drain output mode). in addition, you can configure a pull-up and pull-down resistor to individual pin using control register settings. it is designed for high-current functions such as led direct drive. p1.0, p1.1 are used for oscillator input/output by smart option. also, p1.2 is used for reset pin by smart option. one control register is used to control port 1: p1con (e9h). you address port 1 bits directly by writing or reading the port 1 data register, p1 (e1h). when you use external oscillator, p1.0, p1.1 must be set to output port to prevent current consumption. v dd in/out output disable (input mode) p1 data v dd pull-up register (50 k w typical) circuit type a input data pull-down enable pull-up enable open-drain mux d0 d1 x in , x out or reset note: i/o pins have protection diodes through v dd and v ss . mux smart option pull-down register (50 k w typical) mode input data output input d0 d1 figure 9-6. port 1 circuit diagram
i/o ports s3c9454b/f9454b 9- 8 port 1 control register e9h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7] port 1.1 n-channel open-drain enable bit 0 = configure p1.1 as a push-pull output 1 = configure p1.1 as a n-channel open-drain output [.6] port 1.0 n-channel open-drain enable bit 0 = configure p1.0 as a push-pull output 1 = configure p1.0 as a n-channel open-drain output [.5-.4] not used for s3c9454b/f9454b [.3-.2] port 1, p1.1 configuration bits 0 0 = schmitt trigger input; 0 1 = schmitt trigger input; pull-up enable 1 0 = push-pull output 1 1 = schmitt trigger input; pull-down enable [.1-.0] port 1, p1.0 configuration bits 0 0 = schmitt trigger input; 0 1 = schmitt trigger input; pull-up enable 1 0 = push-pull output 1 1 = schmitt trigger input; pull-down enable note: when you use external oscillator, p1.0, p1.1 must be set to output port to prevent current consumption. figure 9-7. port 1 control register (p1con)
s3c9454b/f9454b i/o ports 9- 9 port 2 port 2 is a 7-bit i/o port with individually configurable pins. it can be used for general i/o port (schmitt trigger input mode, push-pull output mode or n-channel open-drain output mode). you can also use some pins of port 2 adc input, clo output and t0 clock output. in addition, you can configure a pull-up resistor to individual pins using control register settings. it is designed for high-current functions such as led direct drive. you address port 2 bits directly by writing or reading the port 2 data register, p2 (e2h). the port 2 control register, p2conh and p2conl is located at addresses eah, ebh respectively. v dd in/out output disable (input mode) p0 data v dd pull-up register (50 k w typical) circuit type a input data to adc pull-up enable open-drain mux d0 d1 note: i/o pins have protection diodes through v dd and v ss . m u x mode input data output input d0 d1 clo, t0 p2conh/l figure 9-8. port 2 circuit diagram
i/o ports s3c9454b/f9454b 9- 10 port 2 control register (high byte) eah, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7] not sued for s3c9454b/f9454b [.6-.4] port 2, p2.6/adc8/clo configuration bits 0 0 0 = schmitt trigger input; pull-up enable 0 0 1 = schmitt trigger input 0 1 x = adc input 1 0 0 = push-pull output 1 0 1 = open-drain output; pull-up enable 1 1 0 = open-drain output 1 1 1 = alternative function; clo output [.3-.2] port 2, p2.5 configuration bits 0 0 = schmitt trigger input; pull-up enable 0 1 = schmitt trigger input 1 0 = push-pull output 1 1 = open-drain output [.1-.0] port 2, p2.4 configuration bits 0 0 = schmitt trigger input; pull-up enable 0 1 = schmitt trigger input 1 0 = push-pull output 1 1 = open-drain output note: when noise problem is important issue, you had better not use clo output figure 9-9. port 2 control register (p2conh, high byte)
s3c9454b/f9454b i/o ports 9- 11 port 2 control register (low byte) ebh, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7-.6] port 2, p2.3 configuration bits 0 0 = schmitt trigger input; pull-up enable 0 1 = schmitt trigger input 1 0 = push-pull output 1 1 = open-drain output [.5-.4] port 2, p2.2 configuration bits 0 0 = schmitt trigger input; pull-up enable 0 1 = schmitt trigger input 1 0 = push-pull output 1 1 = open-drain output [.3-.2] port 2, p2.1 configuration bits 0 0 = schmitt trigger input; pull-up enable 0 1 = schmitt trigger input 1 0 = push-pull output 1 1 = open-drain output [.1-.0] port 2, p2.0 configuration bits 0 0 = schmitt trigger input; pull-up enable 0 1 = schmitt trigger input 1 0 = push-pull output 1 1 = t0 match output figure 9-10. port 2 control register (p2conl, low byte)
i/o ports s3c9454b/f9454b 9- 12 notes
s3c9454b/f9454b basic timer and timer 0 10 - 1 1 0 basic timer and timer 0 module overview the s3c9454b/f9454b has two default timers: an 8 - bit basic timer , one 8 - bit general - purpose timer/counter, called timer 0. basic timer (bt) you can use the basic timer (bt) in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release . the functional components of the basic timer block are: ? clock frequency divider (f osc divided by 4096, 1024, or 128) with multiplexer ? 8 - bit basic timer counter, btcnt (ddh, read - only) ? basic timer control register, btcon (dch, read/write) timer 0 timer 0 has the following functional components: ? clock frequency divider (f osc divided by 4096, 256, 8, or f osc ) with multiplexer ? 8 - bit counter (t0cnt), 8 - bit comparator, and 8 - bit data register (t0data) ? timer 0 control register (t0con)
basic timer and timer 0 s3c9454b/f 9454b 10 - 2 basic timer (bt) basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. a reset clears btcon to "00h". this enables the watchdog function and selects a basic timer clock frequency of f osc /4096. to disable the watchdog function, you must write the s ignature code "1010b" to the basic timer register control bits btcon.7 ? btcon.4. the 8 - bit basic timer counter, btcnt, can be cleared during normal operation by writing a "1" to btcon.1. to clear the frequency dividers for both the basic timer input clock a nd the timer 0 clock, you write a "1" to btcon.0. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb basic timer control register (btcon) dch, r/w watchdog timer enable bits: 1010b = disable watchdog function other value = enable watchdog function basic timer counter clear bits: 0 = no effect 1 = clear basic timer counter basic timer input clock selection bits: 00 = fosc/4096 01 = fosc/1024 10 = fosc/128 11 = invalid selection divider clear bit for basic timer and timer 0: 0 = no effect 1 = clear both dividers note: when you write a 1 to btcon.0 (or btcon.1), the basic timer divider (or basic timer counter) is cleared. the bit is then cleared automatically to 0. figure 10 - 1. basic timer control register (btcon)
s3c9454b/f9454b basic timer and timer 0 10 - 3 basic timer function description watchdog timer function you can program the basic timer overflow signal (btovf) to generate a reset by setting btcon.7 ? btcon.4 to any value other than "1010b" (the "1010b" value disables the watchdog function). a reset clears btcon to "00h", automatically enabling the watchdog timer function. a reset also selects the oscillator clock divided by 4096 as the bt clock. a reset whenever a basic timer counter overflow occurs. during normal operation, the application program m ust prevent the overflow, and the accompanying reset operation, from occurring. to do this, the btcnt value must be cleared (by writing a "1" to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error conditi on, the bt counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8 - bit basic timer counter, btcnt) is always b roken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at t he rate of f osc /4096 (for reset), or at the rate of the preset clock source (for an external interrupt). when btcnt.4 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume normal operation. in summary, the following events occur when stop mode is released: 1. during stop mode, a external power - on reset or an external interrupt occurs to trigger the stop mode release and oscillation starts. 2. if a external pow er - on reset occurred, the basic timer counter will increase at the rate of f osc /4096. if an external interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begin s and continues until bit 4 of the basic timer counter is set. 4. when a btcnt.4 is set, normal cpu operation resumes. figure 10 - 2 and 10 - 3 shows the oscillation stabilization time on reset and stop mode release
basic timer and timer 0 s3c9454b/f 9454b 10 - 4 oscillation stabilization time normal operating mode 0.8 v dd t wait = (4096x16)/f osc basic timer increment and cpu operations are idle mode 10000b 00000b reset release voltage note: duration of the oscillator stabilization wait time, t wait , when it is released by a power-on-reset is 4096 x 16/f osc . t rst rc (r and c are value of external power on reset) v dd reset internal reset release oscillator (x out ) btcnt clock btcnt value oscillator stabilization time trst ~ rc ~ ~ ~ 0.8 v dd figure 10 - 2. o scillation stabilization time on reset
s3c9454b/f9454b basic timer and timer 0 10 - 5 note: duration of the oscillator stabilzation wait time, t wait , it is released by an interrupt is determined by the setting in basic timer control register, btcon. v dd oscillation stabilization time reset external interrupt oscillator (x out ) btcnt clock btcnt value t wait basic timer increment 10000b stop release signal 00000b normal operating mode normal operating mode stop mode stop mode release signal stop instruction execution btcon.3 btcon.2 0 0 1 1 0 1 0 1 t wait (4096 x 16)/fosc (1024 x 16)/fosc (128 x 16)/fosc invalid setting t wait (when f osc is 10 mhz) 6.55 ms 1.64 ms 0.2 ms figure 10 - 3. oscillation stabilization time on stop mode release
basic timer and timer 0 s3c9454b/f 9454b 10 - 6 f programming tip ? configuring the basic timer this example sh ows how to configure the basic timer to sample specification. org 0000h vector 00h,int_9454 ; s3c9454b/f9454b has only one interrupt vector ; -------------- << smart option >> org 003ch db 00h ; 003ch, must be initialized to 0 db 00h ; 003dh, must be i nitialized to 0 db 0e7h ; 003eh, enable lvr (2.3 v) db 03h ; 003fh, internal rc (3.2 mhz in v dd = 5 v) ; -------------- << initialize system and peripherals >> org 0100h reset: di ; disable interrupt ld clkcon,#00011000b ; select non - divided cpu cl ock ld sp,#0c0h ; stack pointer must be set ld btcon,#02h ; enable watchdog function ; basic timer clock: f osc /4096 ; basic counter (btcnt) clear ei ; enable interrupt ; -------------- << main loop >> main: ld btcon,#02h ; enable watchdog function ; basic counter (btcnt) clear jr t,main ; ; -------------- << interrupt service routines >> int_9454: ; interrupt enable bit and pending bit check ; ; pending bit clear iret ; end ;
s3c9454b/f9454b basic timer and timer 0 10 - 7 timer 0 timer 0 control regi sters (t0con) the timer 0 control register, t0con, is used to select the timer 0 operating mode (interval timer) and input clock frequency, to clear the timer 0 counter, and to enable the t0 match interrupt. it also contains a pending bit for t0 match interrupts. a reset clears t0con to "00h". this sets timer 0 to normal interval timer mode, selects an input clock frequency of f osc /4096, and disables the t0 match interrupts. the t0 counter can be cleared at any time during normal operation by writing a "1" to t0con.3. note: to use t0 match output(p2.0), t0con.3 must be set to "1". in this case, there can be same delay in the timer operation in case time interval is very important, make t0con.3 "0". timer 0 interrupt pending bit: 0 = no t0 interrupt pending (when read) 0 = clear t0 pending bit (when write) 1 = interrupt is pending (when read) 1 = no effect (when write) .7 .6 .5 .4 .3 .2 .1 .0 lsb msb timer 0 control register d3h, r/w timer 0 input clock selection bits: 00 = fosc/4096 01 = fosc/256 10 = fosc/8 11 = fosc not used for s3c9454b/f9454b timer 0 counter clear bit: 0 = no effect 1 = clear the timer 0 counter (when write) timer 0 interrupt enable bit: 0 = disable t0 interrupt 1 = enable t0 interrupt not used for s3c9454b/f9454b figure 10 - 4. timer 0 control registers (t0con)
basic timer and timer 0 s3c9454b/f 9454b 10 - 8 timer 0 function des cription interval timer mode in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 reference data register, t0data. the match signal generates a timer 0 match interrupt (t0int, vector 00h) and t hen clears the counter. if, for example, you write the value "10h" to t0data, the counter will increment until it reaches "10h". at this point, the timer 0 interrupt request is generated, the counter value is reset and counting resumes. comparator clk data register (t0data) match t0con.3 timer 0 counter clear pnd irq0 (t0int) t0con.1 interrupt enable/disable r (clear) counter (t0cnt) note: t0con.3 is not auto-cleared, you must pay attention when clear pending bit (refer to p10-12) f igure 10 - 5. simplified timer 0 function diagram (interval timer mode)
s3c9454b/f9454b basic timer and timer 0 10 - 9 00h count start t0con.3 1 match match match match match match match compare value (t0data) up counter value (t0cnt) counter clear (t0con.3) interrupt request (t0con.0) t0 match output (p2.0) clear clear clear t0data value change figure 10 - 6. timer 0 timing diagram
basic timer and timer 0 s3c9454b/f 9454b 10 - 10 8-bit up counter (btcnt, read-only) ovf bit 1 reset or stop reset data bus note: during a power-on reset operation, the cpu is idle during the required oscillation stabilization interval (until bit 4 the basic timer counter is set). basic timer control register (write '1010xxxxb' to disable.) basic timer control register timer 0 control register t0cnt (d0h) (read-only) 8-bit comparator t0data buffer data bus data bus match signal bit 3 irq0 bits 7, 6 x in div r 1/4096 1/1024 1/128 bit 0 div r 1/4096 1 1/8 1/256 x in mux mux bits 3, 2 mux t0data (d1h) (read/write) bit 3 bit 1 bit 0 clear match clear when btcnt.4 is set after releasing from reset or stop mode, cpu clock starts. p2.0 p2conl.1-.0 figure 10 - 7. basic timer and timer 0 block diagram
s3c9454b/f9454b basic timer and timer 0 10 - 11 f programming tip1 ? configuring timer 0 (interval mode) the following sample program sets timer 0 to interval timer mode. org 0000h vector 00h,int_9454 ; s3c9454b/f9454b has only one interrupt vector org 003ch db 00h ; 003ch, must be initialized to 0 db 00h ; 003dh, must be initialized to 0 db 0e7h ; 003eh, enable lvr (2.3 v) db 03h ; 003fh, internal rc (3.2 mhz in v dd = 5 v) org 0100h reset: di ; disable interrupt ld btcon,#10100011b ; watchdog disable ld clkcon,#00011000b ; select non - divided cpu clock l d sp,#0c0h ; set stack pointer ld p0conh,#10101010b ; ld p0conl,#10101010b ; p0.0 ? 0.7 push - pull output ld p1con,#00001010b ; p1.0 ? p1.1 push - pull output ld p2conh,#01001010b ; ld p2conl,#10101010b ; p2.0 ? p2.6 push - pull output ; ------------ -- << timer 0 settings >> ld t0data,#50h ; cpu = 3.2 mhz, interrupt interval = 4 msec ld t0con,#01001010b ; f osc /256, timer 0 interrupt enable ei ; ena ble interrupt ; -------------- << main loop >> main: nop ; start main loop call led_display ; sub - block module call job ; sub - block module jr t,main ;
basic timer and timer 0 s3c9454b/f 9454b 10 - 12 f programming tip1 ? configuring timer 0 (interval mode) (continued) led_display: nop ; ; ; ; ret ; job: nop ; ; ; ; ret ; ; -------------- << interrupt service routines >> int_9454: tm t0con,#00000010b ; interrupt enable check jr z,next_chk1 ; tm t0con,#00000001b ; if timer 0 interrupt was occurr ed, jp nz,int_timer0 ; t0con.0 bit would be set. next_chk1: ; interrupt enable bit and pending bit check ; ; iret ; int_timer0: ; timer 0 interrup t service routine and t0con,#1111 0 110b ; pending bit clear iret ; end ;
s3c9454b/f9454b 8-b it pwm 11- 1 1 1 8-bit pwm (pulse width modulation ) overview this microcontroller has the 8-bit pwm circuit. the operation of all pwm circuit is controlled by a single control register, pwmcon. the pwm counter is a 8-bit incrementing counter. it is used by the 8-bit pwm circuits. to start the counter and enable the pwm circuits, you set pwmcon.2 to "1". if the counter is stopped, it retains its current count value; when re-started, it resumes counting from the retained count value. when there is a need to clear the counter you set pwmcon.3 to "1". you can select a clock for the pwm counter by set pwmcon.6?.7. clocks which you can select are f osc /64, f osc /8, f osc /2, f osc /1. function description pwm the 8-bit pwm circuits have the following components: ? 6-bit comparator and extension cycle circuit ? 6-bit reference data register (pwmdata.7?.2) ? 2-bit extension data register (pwmdata.1?.0) ? pwm output pins (p0.6/pwm) pwm counter to determine the pwm module's base operating frequency, the upper 6-bits of counter is compared to the pwm data (pwmdata.7?.2). in order to achieve higher resolutions, the lower 2-bits of the counter can be used to modulate the "stretch" cycle. to control the "stretching" of the pwm output duty cycle at specific intervals, the lower 2-bits of counter value is compared with the pwmdata.1?.0.
8-bit pwm s3c9454b/ f9454b 11- 2 pwm data and extension registers pwm (duty) data registers, located in f2h, determine the output value generated by each 8-bit pwm circuit. to program the required pwm output, you load the appropriate initialization values into the 6-bit reference data register (pwmdata.7?.2) and the 2-bit extension data register (pwmdata.1?.0). to start the pwm counter, or to resume counting, you set pwmcon.2 to "1". a reset operation disables all pwm output. the current counter value is retained when the counter stops. when the counter starts, counting resumes at the retained value. pwm clock rate the timing characteristics of pwm output is based on the f osc clock frequency. the pwm counter clock value is determined by the setting of pwmcon.6?.7. table 11-1. pwm control and data registers register name mnemonic address function pwm data registers pwmdata.7?.2 f2h.7?.2 6-bit pwm basic cycle frame value pwmdata.1?.0 f2h.1?.0 2-bit extension ("stretch") value pwm control registers pwmcon f3h pwm counter stop/start (resume), and pwm counter clock settings pwm function description the pwm output signal toggles to low level whenever the lower 6-bit of counter matches the reference data register (pwmdata.7?.2). if the value in the pwmdata.7?.2 register is not zero, an overflow of the lower 6-bits of counter causes the pwm output to toggle to high level. in this way, the reference value written to the reference data register determines the module's base duty cycle. the value in the upper 2-bits of counter is compared with the extension settings in the 2-bit extension data register (pwmdata.1?.0). this lower 2-bits of counter value, together with extension logic and the pwm module's extension data register , is then used to "stretch" the duty cycle of the pwm output. the "stretch" value is one extra clock period at specific intervals, or cycles (see table 11-2). if, for example, the value in the extension data register is '01b', the 2nd cycle will be one pulse longer than the other 3 cycles. if the base duty cycle is 50 %, the duty of the 2nd cycle will therefore be "stretched" to approximately 51% duty. for example, if you write 10b to the extension data register, all odd-numbered pulses will be one cycle longer. if you write 11h to the extension data register, all pulses will be stretched by one cycle except the 4th pulse. pwm output goes to an output buffer and then to the corresponding pwm output pin. in this way, you can obtain high output resolution at high frequencies.
s3c9454b/f9454b 8-b it pwm 11- 3 table 11-2. pwm output "stretch" values for extension data register (pwmdata.1?.0) pwmdata bit (bit1?bit0) "stretched" cycle number 00 ? 01 2 10 1, 3 11 1, 2, 3 250 ns 250 ns 8 m s 8 m s 250 ns 0h 40h 80h 4 mhz 000000xxb 000001xxb 100000xxb 111111xxb pwm clock: pwm data register values: (pwmdata) figure 11-1. 8-bit pwm basic waveform
8-bit pwm s3c9454b/ f9454b 11- 4 1st 2nd 3th 4th 1st 2nd 3th 4th 500 ns 750 ns 0h 40h 4 mhz 0h 40h pwm clock: 4 mhz 000010xxb pwmdata : 0000 1001b basic waveform extended waveform figure 11-2. 8-bit extended pwm waveform
s3c9454b/f9454b 8-b it pwm 11- 5 pwm control register (pwmcon) the control register for the pwm module, pwmcon, is located at register address f3h. pwmcon is used the 8- bit pwm modules. bit settings in the pwmcon register control the following functions: ? pwm counter clock selection ? pwm data reload interval selection ? pwm counter clear ? pwm counter stop/start (or resume) operation ? pwm counter overflow (8-bit counter overflow) interrupt control a reset clears all pwmcon bits to logic zero, disabling the entire pwm module. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb pwm control register (pwmcon) f3h, reset: 00h pwm input clock selection bits: 00 = f osc /64 01 = f osc /8 10 = f osc /2 11 = f osc /1 not used for s3c9454b/f9454b pwmdata reload interval selection bit: 0 : reload from 8-bit up counter overflow 1: reload from 6-bit up counter overflow pwm counter clear bit: 0 = no effect 1 = clear the pwm counter pwm counter enable bit: 0 = stop counter 1 = start (resume countering) pwm ovf interrupt enable bit: 0 = disable interrupt 1 = enable interrupt pwm ovf interrupt pending bit: 0 = no interrupt pending 0 = clear pending condition (when write) 1 = interrupt pending figure 11-3. pwm control register (pwmcon)
8-bit pwm s3c9454b/ f9454b 11- 6 6-bit comparator "1" when reg > count "1" when reg = count extension control logic extension data buffer pwm extension data register from 8-bit up counter (7:6) from 8-bit up counter (5:0) 6-bit data buffer 6-bit data register (f2h) pwmcon.3 (clear) 8 or 6-bit up counter overflow data bus (7:0) f2h bit7-2 p0.6/pwm 2-bit counter 6-bit counter pwmcon.2 mux f osc /64 f osc f osc /8 f osc /2 pwmcon.6-.7 f2h bit1-0 figure 11-4. pwm functional block diagram
s3c9454b/f9454b 8-b it pwm 11- 7 f programming tip ? programming the pwm module to sample specifications ;--------------<< interrupt vector address >> org 0000h vector 00h,int_9454 ; s3c9454/f9454 has only one interrupt vector ;--------------<< smart option >> org 003ch db 00h ; 003ch, must be initialized to 0. db 00h ; 003dh, must be initialized to 0. db 0e7h ; 003eh, enable lvr (2.3 v) db 03h ; 003fh, internal rc (3.2 mhz in v dd = 5 v) ;--------------<< initialize system and peripherals >> org 0100h reset: di ; disable interrupt ld btcon,#10100011b ; watchdog disable ld p0conh,#10011010b ; configure p0.6 pwm output ld pwmcon,#00000110b ; f osc /64, counter/interrupt enable ld pwmdata,#80h ; ei ; enable interrupt ;--------------<< main loop >> main: ; ; ; ; ; jr t,main ; ;--------------<< interrupt service routines >> int_9454: ; interrupt enable bit and pending bit check tm pwmcon,#00000010b ; interrupt enable check jr z,next_chk1 ; tm pwmcon,#00000001b ; interrupt pending bit check jp nz,int_pwm ; pwmcon's pending bit set --> pwm interrupt next_chk1: iret ;
8-bit pwm s3c9454b/ f9454b 11- 8 f programming tip ? programming the pwm module to sample specifications (continued) int_pwm: ; pwm interrupt service routine and pwmcon,#1111 0 110b ; pending bit clear iret ; end
s3c9454b/f9454b a/d converter 12- 1 1 2 a/d converter overview the 10-bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the nine input channels to equivalent 10-bit digital values. the analog input level must lie between the v dd and v ss values. the a/d converter has the following components: ? analog comparator with successive approximation logic ? d/a converter logic ? adc control register (adcon) ? nine multiplexed analog data input pins (adc0?adc8) ? 10-bit a/d conversion data output register (addatah/l): to initiate an analog-to-digital conversion procedure, you write the channel selection data in the a/d converter control register adcon to select one of the nine analog input pins (adcn, n = 0?8) and set the conversion start or enable bit, adcon.0. the read-write adcon register is located at address f7h. during a normal conversion, adc logic initially sets the successive approximation register to 200h (the approximate half-way point of an 10-bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 10-bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value (adcon.7?4) in the adcon register. to start the a/d conversion, you should set a the enable bit, adcon.0. when a conversion is completed, acon.3, the end-of-conversion (eoc) bit is automatically set to 1 and the result is dumped into the addata register where it can be read. the a/d converter then enters an idle state. remember to read the contents of addata before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note because the adc does not use sample-and-hold circuitry, it is important that any fluctuations in the analog level at the adc0?adc8 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to circuit noise, will invalidate the result.
a/d converter s3c94 54b/f9454b 12- 2 using a/d pins for standard digital input the adc module's input pins are alternatively used as digital input in port 0 and p2.6. a/d converter control register (adcon) the a/d converter control register, adcon, is located at address f7h. adcon has four functions: ? bits 7-4 select an analog input pin (adc0?adc8). ? bit 3 indicates the status of the a/d conversion. ? bits 2-1 select a conversion speed. ? bit 0 starts the a/d conversion. only one analog input channel can be selected at a time. you can dynamically select any one of the ten analog input pins (adc0?adc8) by manipulating the 4-bit value for adcon.7?adcon.4. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb a/d converter control register (adcon) f7h, r/w adc0 (p0.0) adc1 (p0.1) adc2 (p0.2) adc3 (p0.3) adc4 (p0.4) adc5 (p0.5) adc6 (p0.6) adc7 (p0.7) adc8 (p2.6) connected with gnd internally ... connected with gnd internally a/d conversion input pin selection bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 ... 1111 conversion speed selection bits: (note) 00 = f osc /16 (f osc < 10 mhz) 01 = f osc /8 (f osc < 10 mhz) 10 = f osc /4 (f osc < 10 mhz) 11 = f osc /1 (f osc < 4 mhz) end-of-conversion (eco) status bit: 0 = a/d conversion is in progress 1 = a/d conversion complete conversion start bit: 0 = no effect 1 = a/d conversion start note: maximum adc clock input = 4 mhz figure 12-1. a/d converter control register (adcon)
s3c9454b/f9454b a/d converter 12- 3 internal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range v ss to v dd. different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first bit conversion is always 1/2 v dd. a/d converter control register adcon (f7h) adcon.7-.4 m u l t i p l e x e r control circuit + - d/a converter v dd v ss successive approximation circuit analog comparator clock selector adcon.0 (aden) adcon.2-.1 conversion result addatah (f8h) addatal (f9h) to data bus adcon.3 (eoc flag) adc0/p0.0 adc1/p0.1 adc2/p0.2 adc7/p0.7 adc8/p2.6 figure 12-2. a/d converter circuit diagram lsb msb .7 .6 .5 .4 .3 .2 .1 .0 - - - - - - .1 .0 msb lsb addatah addatal figure 12-3. a/d converter data register (addatah/l)
a/d converter s3c94 54b/f9454b 12- 4 50 adc clock 9 8 7 6 5 4 3 2 1 0 set-up time 10 clock privious value addatah (8-bit) + addatal (2-bit) 40 clock valid data conversion start adc0n.0 1 eco addata figure 12-4. a/d converter timing diagram conversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up a/d conversion. therefore, total of 50 clocks are required to complete an 10-bit conversion: with an 10 mhz cpu clock frequency, one clock cycle is 400 ns (4/fosc). if each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit 10-bits + step-up time (10 clock) = 50 clocks 50 clock 400 ns = 20 m s at 10 mhz, 1 clock time = 4/f osc (assuming adcon.2?.1 = 10)
s3c9454b/f9454b a/d converter 12- 5 internal a/d conversion procedure 1. analog input must remain between the voltage range of v ss and v dd. 2. configure the analog input pins to input mode by making the appropriate settings in p0conh, p0conl and p2conh registers. 3. before the conversion operation starts, you must first select one of the nine input pins (adc0?adc8) by writing the appropriate value to the adcon register. 4. when conversion has been completed, (50 clocks have elapsed), the eoc flag is set to ?1?, so that a check can be made to verify that the conversion was successful. 5. the converted digital value is loaded to the output register, addatah (8-bit) and addatal (2-bit), then the adc module enters an idle state. 6. the digital conversion result can now be read from the addatah and addatal register. v ss s3c9454b/ f9454b adc0-adc8 analog input pin v dd 101 x in x out figure 12-5. recommended a/d converter circuit for highest absolute accuracy
a/d converter s3c94 54b/f9454b 12- 6 f programming tip ? configuring a/d converter org 0000h vector 00h,int_9454 ; s3c9454/f9454 has only one interrupt vector org 003ch db 00h ; 003ch, must be initialized to 0 db 00h ; 003dh, must be initialized to 0 db 0e7h ; 003eh, enable lvr (2.3 v) db 03h ; 003fh, internal r c (3.2 mhz in v dd = 5 v) org 0100h reset: di ; disable interrupt ld btcon,#10100011b ; watchdog disable ld p0conh,#11111111b ; configure p0.4?p0.7 ad input ld p0conl,#11111111b ; configure p0.0?p0.3 ad input ld p2conh,#00100000b ; configure p2.6 ad input ei ; enable interrupt ;--------------<< main loop >> main: call ad_conv ; subroutine for ad conversion jr t,main ; ad_conv: ld adcon,#00000001b ; select analog input channel ? p0.0 ; select conversion speed ? f osc /16 ; set conversion start bit nop nop ; if you select conversion speed to f osc /16 nop ; at least three nop must be included
s3c9454b/f9454b a/d converter 12- 7 f programming tip ? configuring a/d converter (continued) conv_loop: tm adcon,#00001000b ; check eoc flag jr z,conv_loop ; if eoc flag=0, jump to conv_loop until eoc flag=1 ld r0,addatah ; high 8 bits of conversion result are stored ; to addatah register ld r1,addatal ; low 2 bits of conversion result are stored ; to addatal register ld adcon,#00010011b ; select analog input channel ? p0.1 ; select conversion speed ? f osc /8 ; set conversion start bit conv_loop2:tm adcon,#00001000b ; check eoc flag jr z,conv_loop2 ld r2,addatah ld r3,addatal ret ; int_9454: ; interrupt enable bit and pending bit check ; ; pending bit clear iret ; end
a/d converter s3c94 54b/f9454b 12- 8 notes
s3c9454b/f9454b electrical data 13- 1 1 3 electrical data overview in this section, the following s3c9454b/f9454b electrical characteristics are presented in tables and graphs: ? absolute maximum ratings ? d.c. electrical characteristics ? a.c. ele ctrical characteristics ? input timing measurement points ? oscillator characteristics ? oscillation stabilization time ? operating voltage range ? schmitt trigger input characteristics ? data retention supply voltage in stop mode ? stop mode release timing when initiated by a reset ? a/d converter electrical characteristics ? lvr circuit characteristics ? lvr reset timing
electrical data s3c 9454b/f9454b 13- 2 table 13-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all ports ? 0.3 to v dd + 0.3 v output voltage v o all output ports ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 25 ma all i/o pins active ? 80 output current low i ol one i/o pin active + 30 ma all i/o pins active + 150 operating temperature t a ? ? 25 to + 85 c storage temperature t stg ? ? 65 to + 150 c
s3c9454b/f9454b electrical data 13- 3 table 13-2. dc electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit input high voltage v ih1 ports 0, 1, 2 and reset v dd = 2.0 to 5.5 v 0.8 v dd ? v dd v v ih2 x in and x out v dd - 0.1 input low voltage v il1 ports 0, 1, 2 and reset v dd = 2.0 to 5.5 v ? ? 0.2 v dd v v il2 x in and x out 0.1 output high voltage v oh i oh = ? 10 ma ports 0, 1, 2 v dd = 4.5 to 5.5 v v dd -1.5 v dd - 0.4 ? v output low voltage v ol i ol = 25 ma port 0, 1, and 2 v dd = 4.5 to 5.5 v ? 0.4 2.0 v input high leakage current i lih1 all input except i lih2 v in = v dd ? ? 1 ua i lih2 x in , x out v in = v dd 20 input low leakage current i lil1 all input except i lil2 v in = 0 v ? ? ?1 ua i lil2 x in , x out v in = 0 v ?20 output high leakage current i loh all output pins v out = v dd ? ? 2 ua output low leakage current i lol all output pins v out = 0 v ? ? ?2 ua pull-up resistors r p v in = 0 v, t a =25 c ports 0, 1, 2 v dd = 5 v 25 50 100 k w pull-down resistors r p v in = 0 v, t a =25 c ports 1 v dd = 5 v 25 50 100 supply current i dd1 run mode 10 mhz cpu clock v dd = 4.5 to 5.5 v ? 5 10 ma 3 mhz cpu clock v dd = 2.0 v 2 5 i dd2 idle mode 10 mhz cpu clock v dd = 4.5 to 5.5 v ? 2 4 3 mhz cpu clock v dd = 2.0 v 0.5 1.5 i dd3 stop mode t a = 25 c v dd = 4.5 to 5.5 v (lvr disable) ? 0.1 5 ua v dd = 4.5 to 5.5 v (lvr enable) 100 200 v dd = 2.6 v (lvr enable) 30 60 note: supply current does not include current drawn through internal pull-up resistors or external output current loads and adc module.
electrical data s3c 9454b/f9454b 13- 4 table 13-3. ac electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input low width t intl int0, int1 v dd = 5 v 10 % ? 200 ? ns reset input low width t rsl input v dd = 5 v 10 % ? 1 ? us t intl t inth x in 0.8 v dd 0.2 v dd figure 13-1. input timing measurement points
s3c9454b/f9454b electrical data 13- 5 table 13-4. oscillator characteristics (t a = ? 25 c to + 85 c) oscillator clock circuit test condition min typ max unit main crystal or ceramic x in x out c1 c2 v dd = 4.5 to 5.5 v 1 ? 10 mhz v dd = 2.7 to 4.5 v 1 ? 6 mhz v dd = 2.0 to 2.7 v 1 ? 3 mhz external clock (main system) x in x out v dd = 4.5 to 5.5 v 1 ? 10 mhz v dd = 2.7 to 4.5 v 1 ? 6 mhz v dd = 2.0 to 2.7 v 1 ? 3 mhz external rc oscillator ? v dd = 5 v ? 4 ? mhz internal rc oscillator ? v dd = 5 v ? 3.2 tolerance:20% at t a =25 c 0.5 table 13-5. oscillation stabilization time (t a = - 25 c to + 85 c, v dd = 2.0 v to 5.5 v) oscillator test condition min typ max unit main crystal f osc > 1.0 mhz ? ? 20 ms main ceramic oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 10 ms external clock (main system) x in input high and low width (t xh , t xl ) 25 ? 500 ns oscillator stabilization t wait when released by a reset (1) ? 2 16 /f osc ? ms wait time t wait when released by an interrupt (2) ? ? ? ms notes: 1. f osc is the oscillator frequency. 2. the duration of the oscillator stabilization wait time, t wait , when it is released by an interrupt is determined by the settings in the basic timer control register, btcon.
electrical data s3c 9454b/f9454b 13- 6 10 mhz cpu clock 6 mhz 1 mhz 1 2 3 4 5 6 7 supply voltage (v) 2 mhz 3 mhz 4 mhz 2.7 5.5 4.5 figure 13-2. operating voltage range v ss a a = 0.2 v dd b = 0.4 v dd c = 0.6 v dd d = 0.8 v dd v dd v out v in b c d 0.3 v dd 0.7 v dd figure 13-3. schmitt trigger input characteristics diagram
s3c9454b/f9454b electrical data 13- 7 table 13-6. data retention supply voltage in stop mode (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2.0 ? 5.5 v data retention supply current i dddr stop mode; v dddr = 2.0 v ? 0.1 5 ua note: supply current does not include current drawn through internal pull-up resistors or external output current loads. data retention mode v dddr execution of stop instrction v dd normal operating mode oscillation stabilization time stop mode t wait reset reset occurs note: t wait is the same as 4096 x 16 x 1/f osc ~ ~ ~ ~ figure 13-4. stop mode release timing when initiated by a reset
electrical data s3c 9454b/f9454b 13- 8 table 13-7. a/d converter electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v, v ss = 0 v) parameter symbol test conditions min typ max unit total accuracy ? v dd = 5.12 v cpu clock = 10 mhz v ss = 0 v ? ? 3 lsb integral linearity error ile 2 ? ? 2 differential linearity error dle 2 ? ? 1 offset error of top eot 2 ? 1 3 offset error of bottom eob 2 ? 1 2 conversion time (1) t con f osc = 10 mhz ? 20 ? m s analog input voltage v ian ? v ss ? v dd v analog input impedance r an ? 2 ? ? mw analog input current i adin v dd = 5 v ? ? 10 m a analog block current (2) i adc v dd = 5 v ? 1 3 ma v dd = 3 v 0.5 1.5 v dd = 5 v power down mode ? 100 500 na notes: 1. ?conversion time? is the time required from the moment a conversion operation starts until it ends. 2. i adc is operating current during a/d conversion.
s3c9454b/f9454b electrical data 13- 9 table 13-8. lvr circuit characteristics (t a = 25 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit low voltage reset v lvr ? 2.0 3.3 3.6 2.3 3.0 3.9 2.6 3.6 4.2 v v dd v lvr,max v lvr v lvr,min figure 13-5. lvr reset timing
electrical data s3c 9454b/f9454b 13- 10 notes
s3c9454b/f9454b mechanical data 14- 1 1 4 mechanical data overview the s3c9454b/f9454b is available in a 20-pin dip package (samsung: 20-dip-300a), a 20-pin sop package (samsung: 20-sop-375), a 20-pin ssop package (samsung: 20-ssop-225), a 16-pin dip package (samsung: 16-dip-300a), a 16-pin sop package (samsung: 16-sop-bd300-sg), a 16-pin ssop package (samsung: 16- ssop-bd44). package dimensions are shown in figure 14-1, 14-2, 14-3, 14-4, 14-5 and 14-6. note : dimensions are in millimeters. 26.80 max 26.40 0 .20 (1.77) 20-dip-300a 6.40 0 .20 #20 #1 0.46 0.10 1.52 0.10 #11 #10 0-15 0.25 + 0.10 - 0.05 7.62 2.54 0.51 min 3.30 0.30 3.25 0.20 5.08 max figure 14-1. 20-dip-300a package dimensions
mechanical data s3c9 454b/f9454b 14- 2 note : dimensions are in millimeters. 20-sop-375 10.30 0 .30 #11 #20 #1 #10 13.14 max 12.74 0 .20 (0.66) 0-8 0.203 + 0.10 - 0.05 9.53 7.50 0.20 0.85 0.20 0.05 min 2.30 0.10 2.50 max 0.40 0.10 max + 0.10 - 0.05 1.27 figure 14-2. 20-sop-375 package dimensions
s3c9454b/f9454b mechanical data 14- 3 note : dimensions are in millimeters. 20-ssop-225 6.40 0 .20 #11 #20 #1 #10 6.90 max 6.50 0 .20 (0.30) 0.05 min 1.50 0.10 1.85 max 0-8 0.15 + 0.10 - 0.05 5.72 4.40 0.10 0.50 0.20 0.10 max +0.10 0.22 -0.05 0.65 figure 14-3. 20-ssop-225 package dimensions
mechanical data s3c9 454b/f9454b 14- 4 note : dimensions are in millimeters. 19.80 max 19.40 0 .20 (0.81) 6.40 0 .20 #16 #1 16-dip-300a 0.46 0.10 1.50 0.10 #9 #8 0-15 0.25 + 0.10 - 0.05 7.62 2.54 0.38 min 3.30 0.30 3.25 0.20 5.08 max figure 14-4. 16-dip-300a package dimensions
s3c9454b/f9454b mechanical data 14- 5 note : dimensions are in millimeters. 16-sop-bd300-sg #9 #16 #1 #8 1.27bsc 0-8 10.10 10.50 10.26 10.56 0.35 0.48 2.35 2.65 0.50 0.75 45 0.23 0.32 0.40 1.27 0.10 0.30 figure 14-5. 16-sop-bd300-sg package dimensions
mechanical data s3c9 454b/f9454b 14- 6 note : dimensions are in millimeters. 16-ssop-bd44 #9 #16 #1 #8 0.252 0.008 6.40 0.20 0.10 max 0.004 max +0.004 0.012 -0.003 +0.10 0.30 -0.07 0.031 0.80 0.002 0.05 min 0.256 0.004 6.50 0.10 +0.004 0.006 -0.002 +0.10 0.15 -0.05 0.019 0.008 0.50 0.20 0.213 5.40 0.173 0.004 4.40 0.10 0.059 0.004 1.50 0.10 0.072 1.85 max 0.018 0.45 figure 14-6. 16-ssop-bd44 package dimensions
s3c9454b/f9454b s3f9 454b mtp 15- 1 1 5 S3F9454B mtp overview the S3F9454B single-chip cmos microcontroller is the mtp (multi time programmable) version of the s3c9454bb/f9454b microcontroller. it has an on-chip flash rom instead of masked rom. the flash rom is accessed by serial data format. the S3F9454B is fully compatible with the s3c9454bb/f9454b, in function, in d.c. electrical characteristics, and in pin configuration. because of its simple programming requirements, the S3F9454B is ideal for use as an evaluation chip for the s3c9454bb/f9454b. v dd / v dd p0.0/adc0/int0/ scl p0.1/adc1/int1/ sda p0.2/adc2 p0.3/adc3 p0.4/adc4 p0.5/adc5 p0.6/adc6/ pwm p0.7/adc7 p2.6/adc8/clo S3F9454B 20 19 18 17 16 15 14 13 12 11 v ss /v ss x in /p1.0 x out /p1.1 v pp / reset /p1.2 t0/p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 1 2 3 4 5 6 7 8 9 10 note: the bolds indicate mtp pin name. figure 15-1. pin assignment diagram (20-pin package)
S3F9454B mtp s3c9454 b/f9454b 15- 2 S3F9454B v dd / v dd p0.0/adc0/int0/ scl p0.1/adc1/int1/ sda p0.2/adc2 p0.3/adc3 p0.4/adc4 p0.5/adc5 p0.6/adc6/ pwm 16 15 14 13 12 11 10 9 v ss /v ss x in /p1.0 x out /p1.1 v pp / reset /p1.2 t0/p2.0 p2.1 p2.2 p2.3 1 2 3 4 5 6 7 8 note: the bolds indicate mtp pin name. figure 15-2. pin assignment diagram (16-pin package)
s3c9454b/f9454b s3f9 454b mtp 15- 3 table 15-1. descriptions of pins used to read/write the flash rom main chip during programming pin name pin name pin no. i/o function p0.1 sda 18 (20-pin) 14 (16-pin) i/o serial data pin (output when reading, input when writing) input and push-pull output port can be assigned p0.0 scl 19 (20-pin) 15 (16-pin) i serial clock pin (input only pin) reset, p1.2 v pp 4 i power supply pin for flash rom cell writing (indicates that mtp enters into the writing mode). when 12.5 v is applied, mtp is in writing mode and when 5 v is applied, mtp is in reading mode. (option) v dd /v ss v dd /v ss 20 (20-pin), 16 (16-pin) 1 (20-pin), 1 (16-pin) i logic power supply pin. table 15-2. comparison of S3F9454B and s3c9454b features characteristic S3F9454B s3c9454b program memory 4 kbyte flash rom 4k byte mask rom operating voltage (v dd ) 2.0 v to 5.5 v 2.0 v to 5.5 v mtp programming mode v dd = 5 v, v pp = 12.5 v pin configuration 20 dip/20 sop/20 ssop/16 dip/16sop/16 ssop/8 dip/8 sop eprom programmability user program multi time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp pin of the S3F9454B flash rom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 15-3 below. table 15-3. operating mode selection criteria v dd v pp reg/mem address (a15?a0) r/w mode 5 v 5 v 0 0000h 1 flash rom read 12.5 v 0 0000h 0 flash rom program 12.5 v 0 0000h 1 flash rom verify 12.5 v 1 0e3fh 0 flash rom read protection note: "0" means low level; "1" means high level.
S3F9454B mtp s3c9454 b/f9454b 15- 4 notes
s3c9454b/f9454b development tools 16- 1 1 6 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that employs win95/98/2000 as its operating system can be used. a sophisticated debugging tool is provided both hardware and software: the powerful in-circuit emulator, smds2+ or sk-1000, for s3c7, s3c9, s3c8 families of microcontrollers. the smds2+ is a new and improved version of smds2, and sk-1000 is supported by a third party tool vendor. samsung also offers support software that includes debugger, assembler, and a program for setting options. shine samsung host interface for in-circuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm86 the sasm86 is an relocatable assembler for samsung's s3c9-series microcontrollers. the sasm86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm86 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value "ff" is filled into the unused rom area upto the maximum rom size of the target device automatically.
development tools s 3c9454b/f9454b 16- 2 target boards target boards are available for all s3c9-series microcontrollers. all required target system cables and adapters are included with the device-specific target board. mtp s multi times programmable microcontrollers (mtps) are under development for s3c9454b/f9454b microcontroller. bus emulator (smds2+ or sk-1000) rs-232c pod probe adapter eprom writer unit ram break/display unit trace/timer unit sam8 base unit power supply unit ibm-pc at or compatible tb9454b target board eva chip target application system figure 16-1. smds2+ or sk-1000 product configuration
s3c9454b/f9454b development tools 16- 3 tb9454b target board the tb9454b target board is used for the s3c9454b/f9454b microcontrollers. it is supported by the sk1000/smds2+ development systems. tb9454b sm1333a gnd v cc + idle + stop 20 1 10 11 100-pin connector 25 1 reset to user_v cc off on u2 external triggers ch1 ch2 128 qfp s3e9450 eva chip j101 smds smds2+ cn1 1 24 20-pin connector 8 pin dip switch figure 16-2. tb9454b target board configuration
development tools s 3c9454b/f9454b 16- 4 table 16-1. power selection settings for tb9454b "to user_vcc" settings operating mode comments to user_vcc off on target system sk-1000/smds2+ tb9454b v cc v ss v cc external the sk1000/smds2+ main board supplies v cc to the target board (evaluation chip) and the target system. on to user_vcc off target system sk-1000/smds2+ tb9454b v cc v ss v cc external the sk1000/smds2+ main board supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. note : the following symbol in the "to user_vcc" setting column indicates the electrical short (off) configuration: smds2+ selection (sam8) in order to write data into program memory that is available in smds2+, the target board should be selected to be for smds2+ through a switch as follows. otherwise, the program memory writing function is not available. table 16-2. the smds2+ tool selection setting "sw1" setting operating mode smds smds2+ target system smds2+ r/w* r/w*
s3c9454b/f9454b development tools 16- 5 table 16-3. using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the sk-1000/smds2+ breakpoint and trace functions. 3eh.7 3eh.6 3eh.5 3eh.4 3eh.3 3eh.2 3fh.1 3fh.0 off on on off low high note: about eva chip, smart option is determined by dip switch not software. figure 16-3. dip switch for smart option
development tools s 3c9454b/f9454b 16- 6 j101 20-pin dip socket 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 v ss p1.0 p1.1 reset / p1.2 t0/p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 v dd p0.0/adc0/int0 p0.1/adc1/int1 p0.2/adc2 p0.3/adc3 p0.4/adc4 p0.5/adc5 p0.6/adc6/pwm p0.7/adc7 p2.6/adc8/clo figure 16-4. 20-pin connector for tb9454b target board 20-pin connector target system j101 1 20 10 11 part name: as20d order cods: sm6304 1 20 10 11 20-pin connector figure 16-5. s3c9454b/f9454b probe adapter for 20-dip package

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